Problem 0. The following table gives some of the parameters for a number of different hardware caches. Fill in the table with the values of the missing parameters. Recall that m is the number of physical address bits, C is the cache size in bytes, B is the block size in bytes, E is the associativity, i.e., lines per set, S is the number of sets, t is the number of tag bits, s is the number of set index bits, and b is the number of block offset bits.

Problem 0. The following table gives some of the parameters for a number of different hardware caches. Fill in the table with the values of the missing parameters. Recall that m is the number of physical address bits, C is the cache size in bytes, B is the block size in bytes, E is the associativity, i.e., lines per set, S is the number of sets, t is the number of tag bits, s is the number of set index bits, and b is the number of block offset bits.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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.2: Below is a list of 32-bit memory address references, given as word addresses. 3, 180, 43, 2, 191, 88, 253 For each of these references, identify the binary address, the tag, and the index given a direct- mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 2-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 4-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty.
In designing a computer’s cache system, the cache block or cache line size is an important parameter. Which of the following statements is correct in this context? A smaller block size implies better spatial locality A smaller block size implies a smaller cache tag and hence lower cache tag overhead A smaller block size implies a larger cache tag and hence lower cache hit time A smaller bock size incurs a lower cache miss penalty
The following table gives the parameters for a number of different caches. For each cache, determine the number of cache sets (S), tag bits (t), set index bits (s), and block offset bits (b). Drag the appropriate labels to their respective targets. Note: not all labels will be used. Reset Help 1 0 2 3 4 5 6 7 8 9 10 15 11 12 13 20 21 22 24 27 28 29 30 31 32 38 48 128 218 256 Cache BE 1. 4 1 2. 8 4 3. 32 32 m C 32 1,024 32 1,024 32 1,024 S 1000 t 음 b 1000 1000 14 220
4. Suppose a computer using a fully associative cache has 2^24 byte of byte-addressable main memory and a cache of 128 blocks, where each block contains 64 bytes. a) How big in kilobytes is main memory? b) How big in bytes is cache? In kilobytes? c) How many blocks of main memory are there? d) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields? e) To which cache block will the memory address 0x01D8729A map?
For a direct-mapped cache with 64KİB data, 8-word blocks, and 32-bit addresses, answer the following questions: a) What is the number of blocks/lines in the cache? b) Identify the bits in the 32-bit address that are used as index bits? c) Identify the bits in the 32-bit address that are used as tag bits? d) What is the total number of bits in this cache (including tag field and valid field)? e) Identify the block number in the cache to which the following 32-bit memory address maps: Ox00003Z00 (Hexadecimal notation) where Z is the least significant digit in your student ID (written as a decimal number)
QUESTION 2 Suppose a computer using direct mapped cache is using 216 (64K) bytes of byte-addressable main memory, and a cache size of 4096 bytes, where each cache block contains 256 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by cache, i.e. what are the length of the tag, block, and offset fields? c) Given memory address 2B9D (in hexadecimal format), which block in the cache will be searched? (What is that block's id?)
A computer of 32 bits has a cache memory of 64 KB with a cache line size of 64 bytes. The cache access time is 20 ns, and the miss penalty is 120 ns. The cache is 2-way associative. a) What is the number of cache lines? b) What is the number of cache sets? c) What is the number of lines per set? d) Draw a scheme of this cache. e) Calculate the time to read a word in case of miss.
Exercise 1: Consider a word-addressable memory of 16 GB, where each word is composed of 128 bits. This memory is directly mapped to a cache of 1 MB composed of blocks where each block contains 16 words. a) What is length (in bits) of the address provided by the processor? b) What is the length (in Bytes) of one memory block? c) How many lines does the cache have? d) What is the length (in bits) of each of the TAG, LINE, and OFFSET? e) Which line in cache can hold the address 00000FOF?
Below is a series of byte addresses in a system with 32 bit words. Assuming a direct-mapped cache with 4-word blocks and a total size of 32 words that is initially empty, (a) label each reference in the list as a hit or a miss and (b) show the entire history of the cache, including tag and data. Byte Address Byte Address (Hexadecimal) (Binary) Hit/Miss 76 0000 0000 0111 0110 1E3 0000 0001 1110 0011 815 0000 1000 0001 0101 141 0000 0001 0100 0001 170 0000 0001 0111 0000 5E1 0000 0101 1110 0001 320 0000 0011 0010 1100 B10 0000 1011 0001 0000 175 0000 0001 0111 0101 583 0000 0101 1000 0011 1FF 0000 0001 1111 1111 7A 0000 0000 0111 1010 2B2 0000 0010 1011 0010 5E4 0000 0101 1110 0100 816 0000 1000 0001 0110 438 0000 0100 0011 1000
A computer is using a fully associative cache and has 216 bytes of main memory (byte addressable) and a cache of 64 blocks, where each block contains 32 bytes. a. How many blocks of main memory are there? b. What will be the sizes of the tag, index, and byte offset fields? c. To which cache set will the memory address 0xF8C9(hexadecimal) map?
3. The table below represents five lines from a cache that uses fully associative mapping with a block size of 8. Identify the address of the shaded data, 0xE6, first in binary and then in hexadecimal. The tag numbers and word id bits are in binary, but the content of the cache (the data) is in hexadecimal. Word id bits Tag 000 001 010 011 100 101 110 111 ------------------------------------------ 1011010 10 65 BA 0F C4 19 6E C3 1100101 21 76 CB 80 D5 2A 7F B5 0011011 32 87 DC 91 E6 3B F0 A6 1100000 43 98 ED A2 F7 4C E1 97 1111100 54 9A FE B3 08 5D D2 88
Assume that you have a direct-mapped cache with 16 indices and each block can contain 32 words. Assuming that each bytes address is 32 bits long (and a word is 32 bits), answer the following questions: a). How many bits in each address are used for its tag? bits b). Compute the total number of bits required to implement this cache, including valid bits, tag bits and bits used for data. bits