For a direct-mapped cache design with 64-bit addresses, the following bits of the address are used to access the cache: Tag  Index Offset 63-13 12-4 3-0 a.  What is the cache block size (in bytes)? b.  What is the cache size (in bytes)? c.  What is the total number of bits (including valid bit, tag bits and data array bits) to implement this cache?

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Q: The phrases "unified cache" and "Hadley cache" should be defined.

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