7. Show the final data and tags of the direct-mapped cache shown below for the given memory contents and data access sequence. As shown, you have 8-bit addresses and 4 bytes of data in each block. You can assume write-through and write-allocate write strategies on write hits and misses respectively. Data Access Sequence Address Data Op. lw BEEEEEEE L SW SW lw lw lw hits = 00 01 11 00 00 10 10 00 00 10 01 00 00 01 00 00 00 11 01 00 00 10 10 00 00 01 11 00 00 10 01 00 00 10 00 00 00 10 10 00 misses = 32 642 124 I 00 01 10 11 Direct-Mapped Cache V Tag Data hit rate= miss rate = Memory Address 00 00 10 00 00 00 11 00 00 01 00 00 00 01 01 00 00 01 10 00 00 01 11 00 00 10 00 00 00 10 01 00 00 10 10 00 00 10 11 00 00 11 00 00 00 11 01 00 Data 435 9 47 13 7586 86 43 48 673 4 972 1003

7. Show the final data and tags of the direct-mapped cache shown below for the given memory contents and data access sequence. As shown, you have 8-bit addresses and 4 bytes of data in each block. You can assume write-through and write-allocate write strategies on write hits and misses respectively. Data Access Sequence Address Data Op. lw BEEEEEEE L SW SW lw lw lw hits = 00 01 11 00 00 10 10 00 00 10 01 00 00 01 00 00 00 11 01 00 00 10 10 00 00 01 11 00 00 10 01 00 00 10 00 00 00 10 10 00 misses = 32 642 124 I 00 01 10 11 Direct-Mapped Cache V Tag Data hit rate= miss rate = Memory Address 00 00 10 00 00 00 11 00 00 01 00 00 00 01 01 00 00 01 10 00 00 01 11 00 00 10 00 00 00 10 01 00 00 10 10 00 00 10 11 00 00 11 00 00 00 11 01 00 Data 435 9 47 13 7586 86 43 48 673 4 972 1003

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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3. Caching In this question, let's assume that we have a 16-bit system with a single level 6-way set associative cache with 8 sets, and a cache block size of 64 bytes. How many bits are needed for the setID and the tags? Draw the breakdown of the tag/index/byte- in-block bits. What is the total size of this cache? For the following program, assume that an integer is 4 bytes. int i; // Assume these variables are stored in the registers. int a[65536]; // Assume that a = 0x1000 int b[65536]; // Assume that b = 0x8000000 for (i=0; i<1024; i++) a[i* 8 ] = i; for (i=0; i<1024; i++) b[i * 8 ] = a[i * 8 ]++; Let's asssume that the array is initialized to zero and that the variable i is already stored on the register. What is my cache hit rate? Show your work.
For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. a. What is the cache block size in words? b. How many entries does the cache have? Tag 31-13 Index 12-6 Offset 5-0
1. Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses. 42, 137, 66, 50, 38, 225, 173, 22, 19, 88, 51, 43 a. For each of these references, identify the binary address, the tag, and the index given a direct mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. b. For each of these references, identify the binary address, the tag, and the index given a direct mapped cache with two-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. Please explain the process.
.2: Below is a list of 32-bit memory address references, given as word addresses. 3, 180, 43, 2, 191, 88, 253 For each of these references, identify the binary address, the tag, and the index given a direct- mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 2-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 4-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty.
A 2-way set associative cache consists of four sets. Main memory contains 2K blocks of eight words each. Show the main memory address format that allows us to map addresses from main memory to cache. Be sure to include the fields as well as their sizes. Compute the hit ratio for a program that loops 6 times from locations 8 to 51 in main memory. You may leave the hit ratio in terms of a fraction. Please show details how you obtain the result.
For a direct-mapped cache with 64KİB data, 8-word blocks, and 32-bit addresses, answer the following questions: a) What is the number of blocks/lines in the cache? b) Identify the bits in the 32-bit address that are used as index bits? c) Identify the bits in the 32-bit address that are used as tag bits? d) What is the total number of bits in this cache (including tag field and valid field)? e) Identify the block number in the cache to which the following 32-bit memory address maps: Ox00003Z00 (Hexadecimal notation) where Z is the least significant digit in your student ID (written as a decimal number)
QUESTION 2 Suppose a computer using direct mapped cache is using 216 (64K) bytes of byte-addressable main memory, and a cache size of 4096 bytes, where each cache block contains 256 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by cache, i.e. what are the length of the tag, block, and offset fields? c) Given memory address 2B9D (in hexadecimal format), which block in the cache will be searched? (What is that block's id?)
We are given a list of 64-bit memory address references, given as word addresses. Ox03, Oxb4, Ox2b, 0x02, Oxbf, Ox58, Oxbe, OxOe, Oxb5, Ox2c, Oxba, Oxfd (A) For each of these references, identify the binary word address, the tag, and the index given a direct-mapped cache with 16 one-word blocks. Also list whether each reference is a hit or a miss, assuming the cache is initially empty. (B) For each of these references, identify the binary word address, the tag, the index, and the offset given a direct-mapped cache with two- word blocks and a total size of eight blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. (C) You are asked to optimize a cache design for the given references (i.e. addresses). There are three direct-mapped cache designs possible, all with a total of eight words of data: (i) Cache1 has 1-word blocks, (ii) Cache2 has 2-word blocks, and (iii) Cache3 has 4-word blocks.
Below is a series of byte addresses in a system with 32 bit words. Assuming a direct-mapped cache with 4-word blocks and a total size of 32 words that is initially empty, (a) label each reference in the list as a hit or a miss and (b) show the entire history of the cache, including tag and data. Byte Address Byte Address (Hexadecimal) (Binary) Hit/Miss 76 0000 0000 0111 0110 1E3 0000 0001 1110 0011 815 0000 1000 0001 0101 141 0000 0001 0100 0001 170 0000 0001 0111 0000 5E1 0000 0101 1110 0001 320 0000 0011 0010 1100 B10 0000 1011 0001 0000 175 0000 0001 0111 0101 583 0000 0101 1000 0011 1FF 0000 0001 1111 1111 7A 0000 0000 0111 1010 2B2 0000 0010 1011 0010 5E4 0000 0101 1110 0100 816 0000 1000 0001 0110 438 0000 0100 0011 1000
A computer is using a fully associative cache and has 216 bytes of main memory (byte addressable) and a cache of 64 blocks, where each block contains 32 bytes. a. How many blocks of main memory are there? b. What will be the sizes of the tag, index, and byte offset fields? c. To which cache set will the memory address 0xF8C9(hexadecimal) map?
3. The table below represents five lines from a cache that uses fully associative mapping with a block size of 8. Identify the address of the shaded data, 0xE6, first in binary and then in hexadecimal. The tag numbers and word id bits are in binary, but the content of the cache (the data) is in hexadecimal. Word id bits Tag 000 001 010 011 100 101 110 111 ------------------------------------------ 1011010 10 65 BA 0F C4 19 6E C3 1100101 21 76 CB 80 D5 2A 7F B5 0011011 32 87 DC 91 E6 3B F0 A6 1100000 43 98 ED A2 F7 4C E1 97 1111100 54 9A FE B3 08 5D D2 88
Assume that you have a direct-mapped cache with 16 indices and each block can contain 32 words. Assuming that each bytes address is 32 bits long (and a word is 32 bits), answer the following questions: a). How many bits in each address are used for its tag? bits b). Compute the total number of bits required to implement this cache, including valid bits, tag bits and bits used for data. bits