7. Show the final data and tags of the direct-mapped cache shown below for the given memory contents and data access sequence. As shown, you have 8-bit addresses and 4 bytes of data in each block. You can assume write-through and write-allocate write strategies on write hits and misses respectively. Data Access Sequence Address Data Op. lw BEEEEEEE L SW SW lw lw lw hits = 00 01 11 00 00 10 10 00 00 10 01 00 00 01 00 00 00 11 01 00 00 10 10 00 00 01 11 00 00 10 01 00 00 10 00 00 00 10 10 00 misses = 32 642 124 I 00 01 10 11 Direct-Mapped Cache V Tag Data hit rate= miss rate = Memory Address 00 00 10 00 00 00 11 00 00 01 00 00 00 01 01 00 00 01 10 00 00 01 11 00 00 10 00 00 00 10 01 00 00 10 10 00 00 10 11 00 00 11 00 00 00 11 01 00 Data 435 9 47 13 7586 86 43 48 673 4 972 1003

7. Show the final data and tags of the direct-mapped cache shown below for the given memory contents and data access sequence. As shown, you have 8-bit addresses and 4 bytes of data in each block. You can assume write-through and write-allocate write strategies on write hits and misses respectively. Data Access Sequence Address Data Op. lw BEEEEEEE L SW SW lw lw lw hits = 00 01 11 00 00 10 10 00 00 10 01 00 00 01 00 00 00 11 01 00 00 10 10 00 00 01 11 00 00 10 01 00 00 10 00 00 00 10 10 00 misses = 32 642 124 I 00 01 10 11 Direct-Mapped Cache V Tag Data hit rate= miss rate = Memory Address 00 00 10 00 00 00 11 00 00 01 00 00 00 01 01 00 00 01 10 00 00 01 11 00 00 10 00 00 00 10 01 00 00 10 10 00 00 10 11 00 00 11 00 00 00 11 01 00 Data 435 9 47 13 7586 86 43 48 673 4 972 1003

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Similar questions

Suppose a byte-addressable computer using set associative cache has 8M byes of main memory and a cache of 128 blocks, where each cache block contains 64 bytes. a) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 16-way set associative, what is the format of a memory address as seen by the cache
c) The table below represents 10 lines from a 256 line cache that uses direct mapping with a block size of 4 words. Identify the address of the shaded data (8C16). 3 Line# Tag Word 10 Word 11 Word Word 00 01 110101 12 34 56 78 1 010101 54 32 6A D3 2 000111 8C A2 BC 29 ED F3 001100 33 20 C8 FO 110011 9A D8
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4. Assume 32 bit memory addresses, which are byte addresses. You have a direct-mapped cache with a block size of 8 bytes, and a size of 128 blocks. How many bits will the index, block offset, and tag be? How many total bits are required for the cache, including the data?
Assume the processor sends an incomplete request to the cache while a block is being returned from the write buffer to main memory. The following sequence of events should occur.
1. Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses. 42, 137, 66, 50, 38, 225, 173, 22, 19, 88, 51, 43 a. For each of these references, identify the binary address, the tag, and the index given a direct mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. b. For each of these references, identify the binary address, the tag, and the index given a direct mapped cache with two-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. Please explain the process.
The memory access time is I nanosecond for read operation with a hit in cache. * nanoseconds for a read operation with a miss in cache, 2 nanoseconds for a write operation with a hit in cache and 10 anoseconds for a write operation with a miss in cache. Execution of a sequence of instructions involves 100 instruction fetch operations, 60 memory operand read operations and 40 memory operand write operations. The cache hit-ratio is 0.9. The average memory access time (in nanoseconds) in executing the sequence of instructions is
.2: Below is a list of 32-bit memory address references, given as word addresses. 3, 180, 43, 2, 191, 88, 253 For each of these references, identify the binary address, the tag, and the index given a direct- mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 2-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 4-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty.
When the processor receives a request that it cannot fulfill from the cache, it sends a write buffer to return the unsatisfied block to main memory. So, what ought to be done here?
P2
Below is a series of byte addresses in a system with 32 bit words. Assuming a direct-mapped cache with 4-word blocks and a total size of 32 words that is initially empty, (a) label each reference in the list as a hit or a miss and (b) show the entire history of the cache, including tag and data. Byte Address Byte Address (Hexadecimal) (Binary) Hit/Miss 76 0000 0000 0111 0110 1E3 0000 0001 1110 0011 815 0000 1000 0001 0101 141 0000 0001 0100 0001 170 0000 0001 0111 0000 5E1 0000 0101 1110 0001 320 0000 0011 0010 1100 B10 0000 1011 0001 0000 175 0000 0001 0111 0101 583 0000 0101 1000 0011 1FF 0000 0001 1111 1111 7A 0000 0000 0111 1010 2B2 0000 0010 1011 0010 5E4 0000 0101 1110 0100 816 0000 1000 0001 0110 438 0000 0100 0011 1000
3. The table below represents five lines from a cache that uses fully associative mapping with a block size of 8. Identify the address of the shaded data, 0xE6, first in binary and then in hexadecimal. The tag numbers and word id bits are in binary, but the content of the cache (the data) is in hexadecimal. Word id bits Tag 000 001 010 011 100 101 110 111 ------------------------------------------ 1011010 10 65 BA 0F C4 19 6E C3 1100101 21 76 CB 80 D5 2A 7F B5 0011011 32 87 DC 91 E6 3B F0 A6 1100000 43 98 ED A2 F7 4C E1 97 1111100 54 9A FE B3 08 5D D2 88