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list of 32-bit memory address references, given as words: 3, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253 You are now asked to optimize a cache design for the specified references. There are three directly mapped cache designers possible, all with a total of 8 data words: C1 has 1-word blocks, C2 has 2-word blocks and C3 has 4-word blocks. a) Identify the binary address, tag and index of each of the memory references when using C1, C2 and C3. Tip! Automate the calculations e.g. with Excel or Python and present the results in a table. But also justify why it is the way it is. b) When it comes to miss rate, which cache design is best? c) If the stable time for a miss is 25 cycles, and C1 has an access time of 2 cycles, C2 3 cycles and C3 5 cycles, which is the best cache design?

list of 32-bit memory address references, given as words: 3, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253 You are now asked to optimize a cache design for the specified references. There are three directly mapped cache designers possible, all with a total of 8 data words: C1 has 1-word blocks, C2 has 2-word blocks and C3 has 4-word blocks. a) Identify the binary address, tag and index of each of the memory references when using C1, C2 and C3. Tip! Automate the calculations e.g. with Excel or Python and present the results in a table. But also justify why it is the way it is. b) When it comes to miss rate, which cache design is best? c) If the stable time for a miss is 25 cycles, and C1 has an access time of 2 cycles, C2 3 cycles and C3 5 cycles, which is the best cache design?

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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list of 32-bit memory address references, given as words: 3, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253 You are now asked to optimize a cache design for the specified references. There are three directly mapped cache designers possible, all with a total of 8 data words: C1 has 1-word blocks, C2 has 2-word blocks and C3 has 4-word blocks. a) Identify the binary address, tag and index of each of the memory references when using C1, C2 and C3. Tip! Automate the calculations e.g. with Excel or Python and present the results in a table. But also justify why it is the way it is. b) When it comes to miss rate, which cache design is best? c) If the stable time for a miss is 25 cycles, and C1 has an access time of 2 cycles, C2 3 cycles and C3 5 cycles, which is the best cache design?
Transcribed Image Text:list of 32-bit memory address references, given as words: 3, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253 You are now asked to optimize a cache design for the specified references. There are three directly mapped cache designers possible, all with a total of 8 data words: C1 has 1-word blocks, C2 has 2-word blocks and C3 has 4-word blocks. a) Identify the binary address, tag and index of each of the memory references when using C1, C2 and C3. Tip! Automate the calculations e.g. with Excel or Python and present the results in a table. But also justify why it is the way it is. b) When it comes to miss rate, which cache design is best? c) If the stable time for a miss is 25 cycles, and C1 has an access time of 2 cycles, C2 3 cycles and C3 5 cycles, which is the best cache design?
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