Problem 2. The following table gives the parameters for a number of different caches. For each cache, fill in the missing fields in the table. Recall that m is the number of physical address bits, C is the cache size (number of data bytes), B is the block size in bytes, E is the associativity, S is the number of cache sets, t is the number of tag bits, s is the number of set index bits, and b is the number of block offset bits. Cache m C BES tsb 1 32 2048 32 234 2562183 2372 4 4 32 1,024 8 64 256 32 1,024|32|2 16 5

Problem 2. The following table gives the parameters for a number of different caches. For each cache, fill in the missing fields in the table. Recall that m is the number of physical address bits, C is the cache size (number of data bytes), B is the block size in bytes, E is the associativity, S is the number of cache sets, t is the number of tag bits, s is the number of set index bits, and b is the number of block offset bits. Cache m C BES tsb 1 32 2048 32 234 2562183 2372 4 4 32 1,024 8 64 256 32 1,024|32|2 16 5

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

Problem 0. The following table gives some of the parameters for a number of different hardware caches. Fill in the table with the values of the missing parameters. Recall that m is the number of physical address bits, C is the cache size in bytes, B is the block size in bytes, E is the associativity, i.e., lines per set, S is the number of sets, t is the number of tag bits, s is the number of set index bits, and b is the number of block offset bits. Cache m 48 32030 (b) 48 32 24 24 C B E 16384 32 16 32768 64 65536 128 512 32 1024 8 8 4 14 1 4 S b S t
27. Why are the tag bits of a memory address important in a cache memory system? A. The more tag bits there are, the higher the hit ratio. B. The more tag bits there are, the lower the hit ratio. C. The tag bits tell which block of main memory is occupying a cache line. D. The tag bits are needed to tell whether a cache line has been modified or not. E. The tag bits determine which level of cache is closest to the CPU.
Q e
help with part A B AND C.
For a direct-mapped cache design with 32-bit addresses and 32-bit words (data and instructions). the following bits of the address are used to access the cache: Tag = [31:17], Index = [16:5], Offset = [4:0]. a.) What is the cache block size in 32-bit words. b.) How many blocks does the cache have? c.) What is the size of the cache in kilobytes?
Suppose we have a memory and a 2-way set-associative cache with the following characteristics. Memory is byte addressable. Memory addresses are 16 bits. The cache has 64 lines and each cache line holds 8 bytes of data (a) Show the memory address format. Memory address (b) Given a sequence of four binary memory addresses in the order they are used to reference 0010 1101 1011 0011 memory, indicate whether that reference is a hit or a miss. Assume that the cache is initially empty. You need to show the calculation. 0010 1101 1011 1000 0110 1101 1011 0111 1010 1101 1011 1000
Suppose a computer using fully associative cache has 224 words of main memory and a cache of 512 blocks, where each cache block contains 16 words. How many blocks of main memory are there? What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields? To which cache block will the memory reference 17042416 map?
operating system
Suppose a computer using direct mapped cache has 236 bytes of byte-addressable main memory and a cache size of 1024 bytes, and each cache block contains 64 bytes. ⦁ How many blocks of main memory are there? ⦁ What is the format of a memory address as seen by cache, i.e., what are the sizes of the tag, block, and offset fields? ⦁ To which cache block will the memory address 0x13A4576B map?
Consider the following parameters: Parameter q) Width of the data bus Parameter r) Transfer time from Main Memory to Cache Parameter s) Transfer time from Cache to CPU Parameter t) Cache size Parameter u) Block size Which choice below best identifies the parameters that impact the cache hit rate: Parameters q) and r) only Parameters q) and t) only Parameters q), t), and u) only Parameter r), s), and t) only Parameters t), and u) only all of the above none of the above
CA_6 We study the properties of cache memory, and for reasons of easier design and efficient circuits, we assume that the cache capacity is 2i Bytes, and cache line size is 2j Bytes, with i and j being natural numbers: (a) How many bits should the tag field have? And can the tag field contain 0 bit (i.e., be empty)? Elaborate (b) Repeat the above for the index field. (c) Repeat the above for the byte-offset field. (d) Finally, depict a figure showing a cache line, indicate what fields it possibly has, state the possible sizes of these fields, and explain the uses of these fields.
5. suppose a computer using fully associative cache has 224 bytes of byte-addressable main memory and a cache of 128 blocks, where each cache block contains 64 bytes. a) how many blocks of main memory are there? b) what is the format of a memory address as seen by the cache ; that is, what are the size of the tag and offset field. c) To which cache block will the memory address 0x01D872 map?