8.Assume a certain system has an 8-bit address bus. After the system is powered on,the following byte-addressed cache references are recorded.AddressBlock0102a) Fill in the table below to show the block address of each byte address reference.3404316V TagV Tag172316AddressBlockAddressb) Assume the cache is a direct-mapped cache as shown below.35 21Data (4 bytes)Data (4 bytes)1723V TagData (4 bytes)V Tag Data (4 bytes)5 21Fill in the table below to show the outcome of each address reference. Assume the cacis empty at the beginning. Note each data block has 4 bytes.

a) Fill the table below to show the block address for each byte address reference: Address 0 4…

8. Assume a certain system has an 8-bit address bus. After the system is po the following byte-addressed cache references are recorded. Address Address Block Address 0 3 23 17 a) Fill in the table below to show the block address of each byte address reference. 2 3 4 16 0 4 16 V Tag V Tag V Tag V Tag 3 5 21 b) Assume the cache is a direct-mapped cache as shown below. Block 0 1 Data (4 bytes) Data (4 bytes) Data (4 bytes) Data (4 bytes) 17 23 5 21 ference. Assume th

8. Assume a certain system has an 8-bit address bus. After the system is po the following byte-addressed cache references are recorded. Address Address Block Address 0 3 23 17 a) Fill in the table below to show the block address of each byte address reference. 2 3 4 16 0 4 16 V Tag V Tag V Tag V Tag 3 5 21 b) Assume the cache is a direct-mapped cache as shown below. Block 0 1 Data (4 bytes) Data (4 bytes) Data (4 bytes) Data (4 bytes) 17 23 5 21 ference. Assume th

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Concept explainers

Types of database architectures

A Database Architecture represents the Database Management System’s (DBMS) design (schema). The DBMS architecture makes it easy to understand the components involved in the database system and their relations. The DBMS architecture may vary based on the system on which it runs. Some systems contain both client and server machines whereas some run only on a server machine. Based on the architecture, the system can be classified as centralized, decentralized, or hierarchical.

Question

8.
Assume a certain system has an 8-bit address bus. After the system is powered on,
the following byte-addressed cache references are recorded.
Address
Block
0
1
0
2
a) Fill in the table below to show the block address of each byte address reference.
3
4
0
4
3
16
V Tag
V Tag
17
23
16
Address
Block
Address
b) Assume the cache is a direct-mapped cache as shown below.
3
5 21
Data (4 bytes)
Data (4 bytes)
17
23
V Tag
Data (4 bytes)
V Tag Data (4 bytes)
5 21
Fill in the table below to show the outcome of each address reference. Assume the cac
is empty at the beginning. Note each data block has 4 bytes.

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[15] For a direct mapped cache design with 32-bit address, the following bits of the address are used to access the cache Tag 31-10 Index Offset 9-4 3-0 A. Assuming a direct mapped cache a. What is the cache block size? b. What is the cache size? c. How many entries/sets/rows does the cache have? d. Starting from power on, the following byte addressed cache references are recorded: 4, 16, 5, 4, 6, 12 Compute the hit ratio for this sequence of addresses. B. Answer above questions assuming the cache to be a 4-way set associative cache.
Calculate the number of bits used for data and overhead for the following caches A. 64-block/line, direct-mapped, write-through, 8 byte block/line
Assume the address format for a fully-associative cache is as follows: 6 bits 2 bits Tag Offset 8 bits Given the cache directory is as shown in the diagram below, indicate whether the memory reference Ox5E results in a cache hits or a miss. Tag valid Block 000 110110 001 000001 010 000010 011 000101 100 001000 1 101 100010 110 010111 111 110110 O Hit O Miss
4. Assume 32 bit memory addresses, which are byte addresses. You have a direct-mapped cache with a block size of 8 bytes, and a size of 128 blocks. How many bits will the index, block offset, and tag be? How many total bits are required for the cache, including the data?
Please help with detailed explanation for problem C, don't copy solutions from other sources. Consider a byte addressing architecture with 64-bit memory addresses. a)Which bits of the address would be used in the tag, index and offset in a direct-mapped cache with 512 1-word blocks. b)Which bits of the address would be used in the tag, index and offset in a direct-mapped cache with 64 8-word blocks. c)What is the ratio of bits used for storing data to total bits stored in the cache in each of the above cases a and b?
1. Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses. 42, 137, 66, 50, 38, 225, 173, 22, 19, 88, 51, 43 a. For each of these references, identify the binary address, the tag, and the index given a direct mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. b. For each of these references, identify the binary address, the tag, and the index given a direct mapped cache with two-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. Please explain the process.
.2: Below is a list of 32-bit memory address references, given as word addresses. 3, 180, 43, 2, 191, 88, 253 For each of these references, identify the binary address, the tag, and the index given a direct- mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 2-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 4-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty.
QUESTION 2 Suppose a computer using direct mapped cache is using 216 (64K) bytes of byte-addressable main memory, and a cache size of 4096 bytes, where each cache block contains 256 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by cache, i.e. what are the length of the tag, block, and offset fields? c) Given memory address 2B9D (in hexadecimal format), which block in the cache will be searched? (What is that block's id?)
P2
.2: Below is a list of 32-bit memory address references, given as word addresses. 3, 180, 43, 2, 191, 88, 253 For each of these references, identify the binary address, the tag, and the index given a direct- mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 2-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 4-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty.
Question 23 Some portion of cache system A represented below. The system is byte-addressable and the block size is one word (4 bytes). The tag and line number are represented with a binary numbers. The contents of words in the block are represented with hexadecimal. Tag 10 1000 0100 1001 10 1000 0100 1001 10 1000 0100 1001 10 1000 0100 1101 Line Number 0110 1101 0110 1110 0110 1111 B1 FF B8 A1 FF B8 B1 FF B8 A1 FF B8 B1 FF B8 0111 0000 1. What is the size of the main memory of this system? 2. What is the size of the cache memory of this system? 00 Word within block 2016 6116 C116 2116 01 10 11 3216 7216 C216 D216 4216 8216 4116 A216 E216 9216 5216 B216 3. If the CPU requests to read memory address A1 25 BA, what data does the CPU receive? 4. If the CPU requests to read memory address A1 35 C2, what data does the CPU receive? 5. If we access memory in the following order in cache system A: A1 FF B8 how many cache misses would occur for the data request?
The low order 4 bits of the address indicate location in the cache line and the next 4 bits indicate which line in the cache should be used and the remaining bits of the address are used as the cache tag. If the following addresses are read in this order, indicate (circle or similar) each one that would result in a cache miss. 2A1220 2A122C B14408 B14428 2A122C