Question: 32 bytes of memory. 16 bytes of set-associative cache, where blocks can go anywhere within the set. Block is 4 bytes, set in cache is two blocks. Populate memory starting with 0-9, then upper case letters. The following address requests will load the cache: • 00111 • 00001 • 10000 . 10111 • 00011 The CPU then generates address 10110. If this address is in the cache, respond with the requested byte.

Question: 32 bytes of memory. 16 bytes of set-associative cache, where blocks can go anywhere within the set. Block is 4 bytes, set in cache is two blocks. Populate memory starting with 0-9, then upper case letters. The following address requests will load the cache: • 00111 • 00001 • 10000 . 10111 • 00011 The CPU then generates address 10110. If this address is in the cache, respond with the requested byte.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter11: Operating Systems

Section: Chapter Questions

Problem 2VE

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Q2: a cache memory consists of 512 blocks, and if the last word in the block is 1111111. I the last Tag is 1111. Then the total number of words in main memory is Tags, and The main memory consists of blocks. The total number of bits in address fields i . where number of bits for tag field is .... and the remaining number of bits for word field i ..
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Q3) A direct mapped cache has 4 blocks. Each block is 2 words, where a word is 4 bytes. The following load instructions with the given byte addresses are executed sequentially in a program. Calculate the cache block indices for each address and identify whether the load causes a hit or miss. SHOW YOUR CALCULATIONS Hit/Miss Memory Byte Address 11100101 Block Index Tag Ib. 01011101 Ib. 01100110 11011011 lb 11111111
.2: Below is a list of 32-bit memory address references, given as word addresses. 3, 180, 43, 2, 191, 88, 253 For each of these references, identify the binary address, the tag, and the index given a direct- mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 2-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 4-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty.
For a direct-mapped cache design with 64-bit addresses, the following bits of the address are used to access the cache: Tag Index Offset 63-13 12-4 3-0 a. What is the cache block size (in bytes)?b. What is the cache size (in bytes)?c. What is the total number of bits (including valid bit, tag bits and data array bits) to implement this cache?d. For the same block and cache sizes, you want to implement a 4-way set-associative cache, what is the number of index bit and the number of tag bits?
Suppose a computer using direct mapped cache has 232 byte of byte-addressable main memory, and a cache of 1024 blocks, where each cache block contains 32 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag, block, and offset fields? c) To which cache block will the memory address 0x000063FA map?
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instruction is in the first picture cacheSim.h #include<stdlib.h>#include<stdio.h>#define DRAM_SIZE 1048576typedef struct cb_struct {unsigned char data[16]; // One cache block is 16 bytes.u_int32_t tag;u_int32_t timeStamp; /// This is used to determine what to evict. You can update the timestamp using cycles.}cacheBlock;typedef struct access {int readWrite; // 0 for read, 1 for writeu_int32_t address;u_int32_t data; // If this is a read access, value here is 0}cacheAccess;// This is our dummy DRAM. You can initialize this in anyway you want to test.unsigned char * DRAM;cacheBlock L1_cache[2][2]; // Our 2-way, 64 byte cachecacheBlock L2_cache[4][4]; // Our 4-way, 256 byte cache// Trace points to a series of cache accesses.FILE *trace;long cycles;void init_DRAM();// This function print the content of the cache in the following format for an N-way cache with M Sets// Set 0 : CB1 | CB2 | CB 3 | ... | CB N// Set 1 : CB1 | CB2 | CB 3 | ... | CB N// ...// Set M-1 : CB1 | CB2 | CB…
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3. Calculate the physical memory location for each of the following cases? a- The logical address D470H in the extra segment. b- The logical address 2D90H in the stack segment. C- MOV [BP],AL if BP=2C30H. Assume ES=52B9, SS=5D27, DS=E000, and CS=B3FF.
A computer of 32 bits has a cache memory of 64 KB with a cache line size of 64 bytes. The cache access time is 20 ns, and the miss penalty is 120 ns. The cache is 2-way associative. a) What is the number of cache lines? b) What is the number of cache sets? c) What is the number of lines per set? d) Draw a scheme of this cache. e) Calculate the time to read a word in case of miss.