Q3) A direct mapped cache has 4 blocks. Each block is 2 words, where a word is 4 bytes. The following load instructions with the given byte addresses are executed sequentially in a program. Calculate the cache block indices for each address and identify whether the load causes a hit or miss. SHOW YOUR CALCULATIONS Memory Byte Address 11100101 Block Index Tag Hit/Miss Ib. 01011101 Ib 01100110 11011011 11111111

Q3) A direct mapped cache has 4 blocks. Each block is 2 words, where a word is 4 bytes. The following load instructions with the given byte addresses are executed sequentially in a program. Calculate the cache block indices for each address and identify whether the load causes a hit or miss. SHOW YOUR CALCULATIONS Memory Byte Address 11100101 Block Index Tag Hit/Miss Ib. 01011101 Ib 01100110 11011011 11111111

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

A memory system has 4 KB byte-addressable main memory and a direct-mapped cache that consists of 8 blocks with 16 bytes per block. The following shows the main memory address format that allows us to map addresses from main memory to cache. Note: 12 bit address, 4 bit offset, 3 bit $block, and 5 bit tag Assume the cache directory shown below:
A cache system is to be designed to store data from a 256 MB memory space. If each block of main memory contains 16 words, determine the number of blocks that are needed and draw the logical organization of the full address identifying the block ID portion and the word (offset) portion
Suppose a byte-addressable computer using set-associative cache has 216 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes.Q.) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache; that is, what are the sizes of the tag, set, and offset fields?
What differentiates an associative cache from a directly mapped cache is the ability to arbitrarily associate data objects.
4
Consider the following parameters: Parameter q) Width of the data bus Parameter r) Transfer time from Main Memory to Cache Parameter s) Transfer time from Cache to CPU Parameter t) Cache size Parameter u) Block size Which choice below best identifies the parameters that impact the cache hit rate: Parameters q) and r) only Parameters q) and t) only Parameters q), t), and u) only Parameter r), s), and t) only Parameters t), and u) only all of the above none of the above
architecture.
c) The table below represents 10 lines from a 256 line cache that uses direct mapping with a block size of 4 words. Identify the address of the shaded data (8C16). 3 Line# Tag Word 10 Word 11 Word Word 00 01 110101 12 34 56 78 1 010101 54 32 6A D3 2 000111 8C A2 BC 29 ED F3 001100 33 20 C8 FO 110011 9A D8
In a Direct Mapped Cache Memory Physical Address format the Cache line offset field size and word offset field size are same (with word size of one Byte). The number of tag bits in the Physical Address format is equal to the number of blocks in Cache Memory. If the Tag field Size is Mega words. 16 bits, the size of the physical Memory is
List the two main principles used in the design of memory hierarchies and explain them briefly. Briefly describe the read algorithm for reading data from a cache.
Assume the address format for a fully-associative cache is as follows: 6 bits 2 bits Tag Offset 8 bits Given the cache directory is as shown in the diagram below, indicate whether the memory reference Ox5E results in a cache hits or a miss. Tag valid Block 000 110110 001 000001 010 000010 011 000101 100 001000 1 101 100010 110 010111 111 110110 O Hit O Miss
Assume the processor sends an incomplete request to the cache while a block is being returned from the write buffer to main memory. The following sequence of events should occur.