For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache. Tag Index Offset 63-9 8-5 4-0 Beginning from power on, the following byte-addressed cache references are recorded. Нех 00 04 10 84 E8 Ae 400 1E 8C c1c B4 884 (A) For each reference, list (i) its teg, index, and offset, (ii) whether it is a hit or a miss, and (iii) which bytes were replaced (if any). (B) what is the hit ratio? (C) List the final state of the cache, with each valid entry represented as a record of . For example, 3. Memí Øxca01-MemlØxC1F1>

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
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For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache.
Tag
Index
Offset
63-9
8-5
4-0
Beginning from power on, the following byte-addressed cache references are recorded.
Нех
00
04
10 84 E8 AO 400 1E 8C
Cic B4 884
(A) For cach reference, list (i) its teg, index, end offset, (ii) whether it is a hit or a miss, and (iii) which bytes were
replaced (if any).
(B) what is the hit ratio?
(C) List the final state of the cache, with each valid entry represented as a record of <index, tag, data>.
For example,
<e, 3, Mem[ exCe0] -Mem[ØXC1F]>
Transcribed Image Text:For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache. Tag Index Offset 63-9 8-5 4-0 Beginning from power on, the following byte-addressed cache references are recorded. Нех 00 04 10 84 E8 AO 400 1E 8C Cic B4 884 (A) For cach reference, list (i) its teg, index, end offset, (ii) whether it is a hit or a miss, and (iii) which bytes were replaced (if any). (B) what is the hit ratio? (C) List the final state of the cache, with each valid entry represented as a record of <index, tag, data>. For example, <e, 3, Mem[ exCe0] -Mem[ØXC1F]>
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