6. For a direct mapped cache comprising 16 single word blocks answer the following questions. Assume address and word sizes are both 32 bits and that the memory is byte addressed (4 bytes per 32-bit word). Enter answers as numbers only. How many index bits are there? How many offset bits are there? How many tag bits are there?

6. For a direct mapped cache comprising 16 single word blocks answer the following questions. Assume address and word sizes are both 32 bits and that the memory is byte addressed (4 bytes per 32-bit word). Enter answers as numbers only. How many index bits are there? How many offset bits are there? How many tag bits are there?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Software architectures are the blueprint of a software system. They consist of all components involved in a system, relations between various components, the environment of operation, and the principle used in designing the software. In other words, software architecture shows the organization of different software structures and helps understand their behavior.

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Suppose a byte-addressable computer using set-associative cache has 216 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes.Q.) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
CA_6 We study the properties of cache memory, and for reasons of easier design and efficient circuits, we assume that the cache capacity is 2i Bytes, and cache line size is 2j Bytes, with i and j being natural numbers: (a) How many bits should the tag field have? And can the tag field contain 0 bit (i.e., be empty)? Elaborate (b) Repeat the above for the index field. (c) Repeat the above for the byte-offset field. (d) Finally, depict a figure showing a cache line, indicate what fields it possibly has, state the possible sizes of these fields, and explain the uses of these fields.
We are given a list of 64-bit memory address references, given as word addresses. Ox03, Oxb4, Ox2b, Ox02, Oxbf, Ox58, Oxbe, Ox0e, Oxb5, 0x2c, Oxba, Oxfd (A) For each of these references, identify the binary word address, the tag, and the index given a direct-mapped cache with 16 one- word blocks. Also list whether each reference is a hit or a miss, assuming the cache is initially empty. (B) For each of these references, identify the binary word address, the tag, the index, and the offset given a direct-mapped cache with two-word blocks and a total size of eight blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. (C) You are asked to optimize a cache design for the given references (i.e. addresses). There are three direct-mapped cache designs possible, all with a total of eight words of data: (i) Cache1 has 1-word blocks, (ii) Cache2 has 2-word blocks, and (iii) Cache3 has 4-word blocks.
Question 4
.2: Below is a list of 32-bit memory address references, given as word addresses. 3, 180, 43, 2, 191, 88, 253 For each of these references, identify the binary address, the tag, and the index given a direct- mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 2-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 4-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty.
Below is a series of byte addresses in a system with 32 bit words. Assuming a direct-mapped cache with 4-word blocks and a total size of 32 words that is initially empty, (a) label each reference in the list as a hit or a miss and (b) show the entire history of the cache, including tag and data. Byte Address Byte Address (Hexadecimal) (Binary) Hit/Miss 76 0000 0000 0111 0110 1E3 0000 0001 1110 0011 815 0000 1000 0001 0101 141 0000 0001 0100 0001 170 0000 0001 0111 0000 5E1 0000 0101 1110 0001 320 0000 0011 0010 1100 B10 0000 1011 0001 0000 175 0000 0001 0111 0101 583 0000 0101 1000 0011 1FF 0000 0001 1111 1111 7A 0000 0000 0111 1010 2B2 0000 0010 1011 0010 5E4 0000 0101 1110 0100 816 0000 1000 0001 0110 438 0000 0100 0011 1000
3. The table below represents five lines from a cache that uses fully associative mapping with a block size of 8. Identify the address of the shaded data, 0xE6, first in binary and then in hexadecimal. The tag numbers and word id bits are in binary, but the content of the cache (the data) is in hexadecimal. Word id bits Tag 000 001 010 011 100 101 110 111 ------------------------------------------ 1011010 10 65 BA 0F C4 19 6E C3 1100101 21 76 CB 80 D5 2A 7F B5 0011011 32 87 DC 91 E6 3B F0 A6 1100000 43 98 ED A2 F7 4C E1 97 1111100 54 9A FE B3 08 5D D2 88
Consider a cache with 32KİB data, 16-word blocks, and 24-bit addresses, answer the following questions: a) For the direct-mapped configuration, determine the number of index bits and tag bits in the 24-bit address. b) For 4-way set associative configuration, determine the number of index bits and tag bits in the 24-bit address. c) For fully associative contiguration, determine the number of index bits and tag bits in the 24-bit address. d) For an 8-way set associative configuration, identify the set number in the cache to which the following 24-bit memory address maps: Ox001Z00 (Hexadecimal notation) where Z is the least significant digit in your student ID (written as a decimal number)
.2: Below is a list of 32-bit memory address references, given as word addresses. 3, 180, 43, 2, 191, 88, 253 For each of these references, identify the binary address, the tag, and the index given a direct- mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 2-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 4-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty.
Question 23 Some portion of cache system A represented below. The system is byte-addressable and the block size is one word (4 bytes). The tag and line number are represented with a binary numbers. The contents of words in the block are represented with hexadecimal. Tag 10 1000 0100 1001 10 1000 0100 1001 10 1000 0100 1001 10 1000 0100 1101 Line Number 0110 1101 0110 1110 0110 1111 B1 FF B8 A1 FF B8 B1 FF B8 A1 FF B8 B1 FF B8 0111 0000 1. What is the size of the main memory of this system? 2. What is the size of the cache memory of this system? 00 Word within block 2016 6116 C116 2116 01 10 11 3216 7216 C216 D216 4216 8216 4116 A216 E216 9216 5216 B216 3. If the CPU requests to read memory address A1 25 BA, what data does the CPU receive? 4. If the CPU requests to read memory address A1 35 C2, what data does the CPU receive? 5. If we access memory in the following order in cache system A: A1 FF B8 how many cache misses would occur for the data request?
Suppose a computer using fully associative cache has 224 words of main memory and a cache of 512 blocks, where each cache block contains 16 words. How many blocks of main memory are there? What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields? To which cache block will the memory reference 17042416 map?
Consider a 32-bit physical memory space and a 32 KiB 2-way associative cache with LRU replacement. You are told the cache uses 5 bits for the offset field. Write in the number of bits in the tag and index fields. Tag length in bits = Index length in bits =