A CPU has a 32-bit memory address and a 256 KB cache memory. The cache is organized as a 4-way set-associative cache with a cache line size of 16 bytes.
A CPU has a 32-bit memory address and a 256 KB cache memory. The cache is organized as a 4-way set-associative cache with a cache line size of 16 bytes.
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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Transcribed Image Text:A CPU has a 32-bit memory address and a 256 KB cache memory. The cache is
organized as a 4-way set-associative cache with a cache line size of 16 bytes.
Enter numeric values only.
1. What is the number of sets in the cache?
2. What is the size (in bits) of the tag field per cache line?
3. What is the number of comparators required for tag matching?
bits
4. How many address bits are required to find the byte offset within a cache line?
5. What is the total amount of extra memory (in bytes) required for the tag bits?
bytes
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