A cache is organized as a 4 way set associative cache Each set's cache line consists of 4 words (meaning there are 16 bytes per line, for each set of the cache). Each set individually has one Valid bit, and one Dirty bit, for each line. The tag field of this cache is 8 bits wide. The address is 32 bits wide. Question 1c) What is the cache size? (Meaning the number of kilobytes of data being stored in this cache, ignoring the tag, dirty, and valid bits) Question 1d) If this same sized cache (meaning the number of kilobytes of the data part from the question 1c above) are instead organized as a direct mapped cache, what is the total number of 'memory bitcells' needed to design this cache instead (meaning how many bitcells including the tag, dirty, and valid bits? (Assume that the number of cache lines are not changing and that all the bytes of all four sets are now coalesced into one set, thus making it a direct mapped cache)
A cache is organized as a 4 way set associative cache
Each set's cache line consists of 4 words (meaning there are 16 bytes per line, for each set of the cache).
Each set individually has one Valid bit, and one Dirty bit, for each line.
The tag field of this cache is 8 bits wide.
The address is 32 bits wide.
Question 1c) What is the cache size? (Meaning the number of kilobytes of data being stored in this cache, ignoring the tag, dirty, and valid bits)
Question 1d) If this same sized cache (meaning the number of kilobytes of the data part from the question 1c above) are instead organized as a direct mapped cache, what is the total number of 'memory bitcells' needed to design this cache instead (meaning how many bitcells including the tag, dirty, and valid bits? (Assume that the number of cache lines are not changing and that all the bytes of all four sets are now coalesced into one set, thus making it a direct mapped cache)
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