Consider the following parameters: Parameter q) Width of the data bus Parameter r) Transfer time from Main Memory to Cache Parameter s) Transfer time from Cache to CPU Parameter t) Cache size Parameter u) Block size Which choice below best identifies the parameters that impact the cache hit rate: Parameters q) and r) only Parameters q) and t) only Parameters q), t), and u) only Parameter r), s), and t) only Parameters t), and u) only all of the above none of the above

Consider the following parameters: Parameter q) Width of the data bus Parameter r) Transfer time from Main Memory to Cache Parameter s) Transfer time from Cache to CPU Parameter t) Cache size Parameter u) Block size Which choice below best identifies the parameters that impact the cache hit rate: Parameters q) and r) only Parameters q) and t) only Parameters q), t), and u) only Parameter r), s), and t) only Parameters t), and u) only all of the above none of the above

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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A virtual memory has a page size of 16 words. There are 8 pages and 4 blocks. The associative memory page table contains the following entries. (Addresses are given HEX form): Page Block a) For the following virtual addresses find the CPU addresses: 3A, 5B, 1 3 b) For the following CPU addresses find the virtual addresses: 0C, 2D 1 4
A virtual memory has a page size of 8 words. There are 16 pages and 4 blocks. The associative memory page table contains the following entries. (Addresses are given HEX form): Block a) For the following virtual addresses find the CPU addresses: 3B, 54, Page 11 3 3 b) For the following CPU addresses find the virtual addresses: 1A, OC 1 7 2
A 2-way set associative cache consists of four sets. Main memory contains 2K blocks of eight words each. Show the main memory address format that allows us to map addresses from main memory to cache. Be sure to include the fields as well as their sizes. Compute the hit ratio for a program that loops 6 times from locations 8 to 51 in main memory. You may leave the hit ratio in terms of a fraction. Please show details how you obtain the result.
In designing a computer’s cache system, the cache block or cache line size is an important parameter. Which of the following statements is correct in this context? A smaller block size implies better spatial locality A smaller block size implies a smaller cache tag and hence lower cache tag overhead A smaller block size implies a larger cache tag and hence lower cache hit time A smaller bock size incurs a lower cache miss penalty
Operating Systems Problem Two (15 points) Paged page table A paged virtual memory has the following characteristics: The virtual address size is 32 bits. The page size is 1024 words. Each word is 1 integer. Each page table entry needs 4 integers. a) Determine the size of the page table, PT. b) The PT is too large and must be divided into a hierarchy of pages of size 1024 integers. Determine the number of levels in the hierarchy such that no PT exceeds the page size. c) Determine the size of the highest level PT in the hierarchy
4. Suppose a computer using a fully associative cache has 2^24 byte of byte-addressable main memory and a cache of 128 blocks, where each block contains 64 bytes. a) How big in kilobytes is main memory? b) How big in bytes is cache? In kilobytes? c) How many blocks of main memory are there? d) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields? e) To which cache block will the memory address 0x01D8729A map?
5. A computer has an L1 and L2 cache, backed up by DRAM which is backed up by virtual memory. The TLB and L1 caches have hit times of .5 ns. The TLB's backup is the page table in DRAM while L1 cache's backup is an L2 cache. The L2 cache has a hit time of 1.5 ns. DRAM has a hit time of 10 ns. Swap space has a hit time of 2,500,000 ns. The hit rates are: TLB: 98.8%, L1: 91.5%, L2: 97.7%, DRAM: 99.9998% and swap space 100%. What is the effective access time?
Suppose a computer using direct mapped cache has 224 bytes of byte- addressable main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. (Note: 64K = 26 * 210) a) How many blocks of main memory are there? b) What is the format of a memory address as seen by cache, i.e., what are the sizes of the tag, block, and offset fields?
Suppose a computer using fully associative cache has 224 words of main memory and a cache of 512 blocks, where each cache block contains 16 words. How many blocks of main memory are there? What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields? To which cache block will the memory reference 17042416 map?
Suppose a computer using direct mapped cache has 2^24 bytes of byte- addressable main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. (Note: 64K = 26 * 210) a) How many blocks of main memory are there? b) What is the format of a memory address as seen by cache, i.e., what are the sizes of the tag, block, and offset fields?
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Memory system includes the elements: Main Memory=16 Mbytes, Cache=128Kbytes, Block= 8bytes. A) Design a direct-mapped cache memory system. (Draw the block diagram of the cache and mention on the diagram the values of: s, s+w, w, r, s-r) B) For the main memory addresses: 7AF9CD H show the following information, in hexadecimal format: a. Tag, Line, and Word values for a direct-mapped cache. b. Tag and Word values for an associative cache. c. Tag, Set, and Word values for a 4-way set associative cache.