The read access times and the hit ratios for different caches in a memory hierarchy are as given below. Read access time Cache Hit ratio (in nanoseconds) 1-cache 0.8 D-cache 2. 0.9 L2-cache 0.9 The read access time of main memory is 90 nanoseconds. Assume that the caches use the referred-word-first read policy and the write back policy. Assume that all the caches are direct mapped caches. Assume that the dirty bit is always 0 for all the blocks in the

The read access times and the hit ratios for different caches in a memory hierarchy are as given below. Read access time Cache Hit ratio (in nanoseconds) 1-cache 0.8 D-cache 2. 0.9 L2-cache 0.9 The read access time of main memory is 90 nanoseconds. Assume that the caches use the referred-word-first read policy and the write back policy. Assume that all the caches are direct mapped caches. Assume that the dirty bit is always 0 for all the blocks in the

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Concept explainers

Fundamentals of memory

A collection of connected storage devices form the memory unit. It is a space to store data and instructions required for processing. Information is stored in a memory unit in the form of bits. There are two types of memory namely:

Question

1. The read access times and the hit ratios for
different caches in a memory hierarchy are us
given below,
Read access time
Cache
Hit ratio
(in nanoseconds)
I-cache
2.
0.8
D-cache
2.
0.9
L2-cache
0.9
The read access time of main memory is
90 nanoseconds. Assume that the caches use
the referred-w ord-first read policy and the
write back policy. Assume that all the caches
are direct mapped caches. Assume that the
dirty bit is always 0 for all the blocks in the
caches. In execution of a program, 60% cof
memory reads are for instruction fetch and
40% are
for memory operand fetch.
The average read access time in nanoscconds
(up to 2 decimal places) is

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Computer science homework Please help me with this homework question.
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Question 23 Some portion of cache system A represented below. The system is byte-addressable and the block size is one word (4 bytes). The tag and line number are represented with a binary numbers. The contents of words in the block are represented with hexadecimal. Tag 10 1000 0100 1001 10 1000 0100 1001 10 1000 0100 1001 10 1000 0100 1101 Line Number 0110 1101 0110 1110 0110 1111 B1 FF B8 A1 FF B8 B1 FF B8 A1 FF B8 B1 FF B8 0111 0000 1. What is the size of the main memory of this system? 2. What is the size of the cache memory of this system? 00 Word within block 2016 6116 C116 2116 01 10 11 3216 7216 C216 D216 4216 8216 4116 A216 E216 9216 5216 B216 3. If the CPU requests to read memory address A1 25 BA, what data does the CPU receive? 4. If the CPU requests to read memory address A1 35 C2, what data does the CPU receive? 5. If we access memory in the following order in cache system A: A1 FF B8 how many cache misses would occur for the data request?
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