OSI There is a 256 byte, 4-way set associative cache where each cache block contains 16 bytes on a 16 processor with 2*" addressable bytes of memory. Assume that the cache is initially empty (all valid bits are zero). Suppose we are accessing the memory addresses in the order of: Ox0010, Ox0032, Ox03B8, Ox0035, Ox0027, OX00AF. a) How many of these address requests are hits/misses? b) What is the hit ratio? c) How many blocks are replaced?

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OSI There is a 256 byte, 4-way set associative cache where each cache block contains 16 bytes on a 16-bit
addressable bytes of memory. Assume that the cache is initially empty (all valid bits
processor with 216
are zero). Suppose we are accessing the memory addresses in the order of:
Ox0010, Ox0032, Ox03B8, Ox0035, 0x0027, OX00AF.
a) How many of these address requests are hits/misses?
b) What is the hit ratio?
c) How many blocks are replaced?
Transcribed Image Text:OSI There is a 256 byte, 4-way set associative cache where each cache block contains 16 bytes on a 16-bit addressable bytes of memory. Assume that the cache is initially empty (all valid bits processor with 216 are zero). Suppose we are accessing the memory addresses in the order of: Ox0010, Ox0032, Ox03B8, Ox0035, 0x0027, OX00AF. a) How many of these address requests are hits/misses? b) What is the hit ratio? c) How many blocks are replaced?
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