EXERCISE PROBLEM Ex 4.2: For the circuit shown in Figure 4.1, VDD = 3.3 V and RD = 10 ks. The transistor parameters are VTN = 0.4 V, k = 100 μA/V², W/L = 50, and λ= 0.025 V1. Assume the transistor is biased such that IDQ = 0.25 mA. (a) Verify that the transistor is biased in the saturation region. (b) Determine the small- signal parameters gm and ro. (c) Determine the small-signal voltage gain. (Ans. (a) VGsQ = 0.716 V and VDSQ = 0.8 V so that VDS > VDs (sat); (b) gm 1.58 mA/V, ro = 160 ks2; (c) -14.9) Vi VGSQ + - VDD D + VGS RD + VDS vo Figure 4.1 NMOS common- source circuit with time- varying signal source in series with gate dc source
EXERCISE PROBLEM Ex 4.2: For the circuit shown in Figure 4.1, VDD = 3.3 V and RD = 10 ks. The transistor parameters are VTN = 0.4 V, k = 100 μA/V², W/L = 50, and λ= 0.025 V1. Assume the transistor is biased such that IDQ = 0.25 mA. (a) Verify that the transistor is biased in the saturation region. (b) Determine the small- signal parameters gm and ro. (c) Determine the small-signal voltage gain. (Ans. (a) VGsQ = 0.716 V and VDSQ = 0.8 V so that VDS > VDs (sat); (b) gm 1.58 mA/V, ro = 160 ks2; (c) -14.9) Vi VGSQ + - VDD D + VGS RD + VDS vo Figure 4.1 NMOS common- source circuit with time- varying signal source in series with gate dc source
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Transcribed Image Text:EXERCISE PROBLEM
Ex 4.2: For the circuit shown in Figure 4.1, VDD = 3.3 V and RD = 10 ks. The
transistor parameters are VTN = 0.4 V, k = 100 μA/V², W/L = 50, and
λ= 0.025 V1. Assume the transistor is biased such that IDQ = 0.25 mA. (a) Verify
that the transistor is biased in the saturation region. (b) Determine the small-
signal parameters gm and ro. (c) Determine the small-signal voltage gain.
(Ans. (a) VGsQ = 0.716 V and VDSQ = 0.8 V so that VDS > VDs (sat);
(b) gm 1.58 mA/V, ro = 160 ks2; (c) -14.9)
Transcribed Image Text:Vi
VGSQ
+
-
VDD
D
+
VGS
RD
+
VDS
vo
Figure 4.1 NMOS common-
source circuit with time-
varying signal source in
series with gate dc source
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