5. The importance of having a good branch predictor depends on how often conditionalbranches are executed. Together with branch predictor accuracy, this will determinehow much time is spent stalling due to mispredicted branches. In this exercise,assume that the breakdown of dynamic instructions into various instructioncategories is as follows:R-Type50%BEQ15%JMP10%LW15%SW10% Also, assume the following branch predictor accuracies:Always-Not-Taken60%Always-Taken40%2-Bit80%5.1 Stall cycles due to mispredicted branches increase the CPI. What is the extra CPIdue to mispredicted branches with the always-taken predictor? Assume that branchoutcomes are determined in the EX stag, that there are no data hazards, and that nodelay slots are used.5.2 Repeat 5.1 for the "always-not-taken" predictor.45.3 Repeat 5.1 for the 2-bit predictor.5.4 With the 2-bit predictor, what speedup would be achieved if we could convert halfof the branch instructions in a way that replaces a branch instruction with an ALUinstruction? Assume that correctly and incorrectly predicted instructions have thesame chance of being replaced.5.5 With the 2-bit predictor, what speedup would be achieved if we could convert halfof the branch instructions in a way that replaced each branch instruction with twoALU instructions? Assume that correctly and incorrectly predicted instructions havethe same chance of being replaced.5.6 Some branch instructions are much more predictable than others. If we know that80% of all executed branch instructions are easy- to-predict loop-back branches thatare always predicted correctly, what is the accuracy of the 2-bit predictor on theremaining 20% of the branch instructions?

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5. The importance of having a good branch predictor depends on how often conditional branches are executed. Together with branch predictor accuracy, this will determine how much time is spent stalling due to mispredicted branches. In this exercise, assume that the breakdown of dynamic instructions into various instruction categories is as follows: R-Type 50% BEQ JMP 15% 10% LW 15% SW 10%

5. The importance of having a good branch predictor depends on how often conditional branches are executed. Together with branch predictor accuracy, this will determine how much time is spent stalling due to mispredicted branches. In this exercise, assume that the breakdown of dynamic instructions into various instruction categories is as follows: R-Type 50% BEQ JMP 15% 10% LW 15% SW 10%

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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1.a) Explain "Pipeline Scheduling" and "Dynamic Scheduling".1.b)Explain "Static branch prediction" and "dynamic branch prediction".1.c) Explain "Register Renaming".1.d) Explain the "Tomasulo Algorithm".
A program is profiled on a CPU: 20% of all instructions are arithmetic, 40% are load, 20% are store, 20% are conditional branches. On this CPU, loads take 4 cycles, stores 1 cycle, ALU instructions 2 cycle, and branches 3 cycles. Compute the CPI for each instruction and the average CPI for that program on that CPU: Compute the CPI for each instruction (GIVE ANSWERS WITH 2 DECIMAL DIGITS: CPI for loads is CPI for stores is CPI for ALU is CPI for branches is Average CPI is
For sub $rd, $rs, $rtReg[rd] = Reg[rs] + Reg[rt] - Which resources (blocks) perform a useful function for the given instructions? - Use the following diagram for each instruction and trace its flow(use pen or highlighter) for the execution of that instruction. - List the units that are used for each instruction. (I mainly need help with tracing, please and thank you)
5. Pipelined datapath has five stages, ie., instruction fetch (IF), decode (ID), execution (EX), memory (MEM), and write back (WB). It has a hazard detection unit. An instruction will be stalled at the decode stage if any of its operands isn't ready. Consider executing the following code on this datapath (1) At the end of fifth cycle of execution, what instruction will be in each of the pipeline stages? (If there is any "bubble" in the pipeline, please write "NOP" in the corresponding pipeline stage.) (5%) You must write the answer with the following format. instruction IF instruction lw $r2, 10($1) sub $r4, $13, Sr2 add $r5, Sr6, $7 and Sr8, Sr4,$r5 IF ID EX (2) If the datapath has a forwarding unit to resolve the data hazard, what instruction will be in each of the pipeline stages at the end of the fifth cycle? (If there is any "bubble" in the -pipeline, please write "NOP" in the corresponding pipeline stage.) (5%) You must write the answer with the following format: (D MEM EX WB.…
Assuming the same instruction mix listed in Problem 7, what is the average execution time across all instructions?
10. 10. Amdahl's Law is as applicable to software as it is to hardware. An oft-cited programming truism states that a program spends 90% of its time executing 10% of its code. Thus, tuning a small amount of program code can often have an enormous effect on the overall performance of a software product. Determine the overall system speedup if: 1. a) 90% of a program is made to run 10 times as fast (900% faster). 2. b) 80% of a program is made to run 20% faster.
CPI stands for clock cycles per instruction. Speedup from pipelining = (Number of pipeline stages) / (Achieved CPI ). Assume a 5-stage pipeline. Assume that CPI = 1 when there are no pipeline stalls (the ideal case). Now assume that every branch instruction causes a 3 clock cycle stall in the pipeline. Assume that for the program being executed 30% of executed instructions are branch instructions. What speedup from pipelining is achieved by this program?
Determine the effective CPI, MIPS rate, and execution time for this program. Consider two different machines, with two different instruction sets, both of which have a clock rate of 200 MHz. The following measurements are recorded on the two machines running a given set of benchmark programs: Instruction Count (millions) Instruction Type Machine A Arithmetic and logic Load and store Branch Others Machine A Arithmetic and logic Load and store Branch Others 8424 10 9824 Cycles per Instruction 1343 1243 4 a. Determine the effective CPI, MIPS rate, and execution time for each machine. b. Comment on the results.
Assume a 5-stage pipelined CPU (IF – ID – MU- EX – WR) requires following time for different sections: Required time 15 ns Pipeline stages Fetch Unit Decode Unit 10 ns 20 ns Memory Unit Execution Unit 8 ns 15 ns Write back Unit The maximum delay required to transfer contents from one state to another is 2ns. a) Show the time steps of pipelining stages for the first 10 instructions of a program. Assume that Instruction-4 is a conditional loop instruction. If the condition is TRUE, CPU runs instructions: 7 - 9 twice. Please note that a single-port RAM is used with the system, such that CPU read only one data from RAM or save only one data to RAM at a time. Calculate the execution time for the first 10 instructions of a program as well. b) Show the time steps and calculate the execution time for above problem while a multiport RAM is used with the system.
Suppose that we are developing a new version of the AMD Barcelona proces- sor with a 4 GHz clock rate. We have added some additional instructions to the instruction set in such a way that the number of instructions has been reduced by 15% from the values shown for each benchmark in Exercise 1.12. The execution times obtained are shown in the following table. a. Name Execution Time (seconds) Reference Time (seconds) bzip2 700 9650 SPECratio 13.7 1.13.2 [10] In general, these CPI values are larger than those obtained in previous exercises for the same benchmarks. This is due mainly to the clock rate used in both cases, 3 GHz and 4 GHz. Determine whether the increase in the CPI is similar to that of the clock rate. If they are dissimilar, why?
1. Consider a machine running a program with four classes of instructions: A/B/C/D. The program requires 360 seconds, with the number of seconds executing each class as shown in the table below: Instruction Class A B C Time (sec) 100 80 120 60 1.1. By how much is the total execution time changed if the time for class D is reduced by 20% and the time for class C is increased by 10% (assuming no other changes)? 1.2. If we want to reduce the total execution time by 20% by optimizing class A only, what is the target execution time of class A instructions in order to achieve the reduction (assuming all other instructions are not changed)? 1.3. Can the total time be reduced by 25% if we only optimize class B? Use calculation to justify your answer.
E In the following code block(Reference:Q11), you will a set of assembly instructions with corresponding line numbers (line numbers are for informational purpose only and they are not part of the source code). 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 mov edx, 5 dec ecx jmp LABEL1 mov eax, 1 LABEL1: mul edx jmp ecx mov edx, 0678h sub edx, eax jmp DWORD PTR [edx] neg ebx add ecx, ebx mov eax, 0 For each of the conditions/scenario listed below, indicate the corresponding line number (that cause or is associated with the condition/scenario). Enter 0 (Zero) if the condition is not caused by the block of code. 1) Memory indirect jump: type your answer... type your answer... type your answer... type your answer... 2) Register indirect jump: 3) Relative short jump: type your answer... 5) Two's complement type your answer... 4) Relative near jump: 6) Unreachable code