A. The following measurements have been made using an architecture simulator for a processor design that is projected to have a clock rate of 1 GHz. What is the design's CPI? Instruction Frequency of CPI Class Occurrence R-type 1 37% Load 6 25% Branch 4 18% Store 2 20% В. wHow does this compare to using branch prediction to shave 1 cycle off the branch latency, but also increasing the number of cycles a store operation takes by 2 cycles?

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