3. A non-pipelined processor has a clock rate of 2.5GHZand an average CPI of 4. An upgrade to the processor introduces a five-stage pipeline. However, due to internal pipeline delays, such as latch delay, the clock rate of the new processor has to be reduced to2GHz. 3.1 What is the speedup achieved for a typical program? Assume that it consists of 100 instructions. The speedup is the ratio between the two processors in terms of the time required to execute the program.  3.2 What is the MIPS rate for each processor? In case of the pipelined processor, ignore the initial filling up.

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ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
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3. A non-pipelined processor has a clock rate of 2.5GHZand an average CPI of 4. An upgrade to the processor introduces a five-stage pipeline. However, due to internal pipeline delays, such as latch delay, the clock rate of the new processor has to be reduced to2GHz.

3.1 What is the speedup achieved for a typical program? Assume that it consists of 100 instructions. The speedup is the ratio between the two processors in terms of the time required to execute the program.

 3.2 What is the MIPS rate for each processor? In case of the pipelined processor, ignore the initial filling up. 

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