12. Show the final data and tags of the two levels of cache, the given memory contents and data access sequence. Consider 5-bit memory addresses and single byte instructions. Assume that the L1 caches are direct mapped and the L2 cache is fully associative, using LRU for replacement. All caches can place a single byte of data in each block. Also assume that addresses greater than 19 contain instructions whereas addresses smaller than 19 contain data. Access Seq. Op. Adr. FETCH 20 LDRB 15 FETCH 30 LDRB 16 FETCH 31 LDRB 15 FETCH 20 LDRB 17 FETCH 28 LDRB 15 FETCH 30 Tag Tag L1(Instruction) miss rate= LII Cache Data LID Cache Data Tag L1(Data) miss rate= L2 Cache Data L2 miss rate= Memory Adr. Data 14 101 15 126 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 3 86 2 91 5 7 13 4 42 0 76 12 3 29 17

12. Show the final data and tags of the two levels of cache, the given memory contents and data access sequence. Consider 5-bit memory addresses and single byte instructions. Assume that the L1 caches are direct mapped and the L2 cache is fully associative, using LRU for replacement. All caches can place a single byte of data in each block. Also assume that addresses greater than 19 contain instructions whereas addresses smaller than 19 contain data. Access Seq. Op. Adr. FETCH 20 LDRB 15 FETCH 30 LDRB 16 FETCH 31 LDRB 15 FETCH 20 LDRB 17 FETCH 28 LDRB 15 FETCH 30 Tag Tag L1(Instruction) miss rate= LII Cache Data LID Cache Data Tag L1(Data) miss rate= L2 Cache Data L2 miss rate= Memory Adr. Data 14 101 15 126 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 3 86 2 91 5 7 13 4 42 0 76 12 3 29 17

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Answer part d only
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