1. cache behavior Consider an overly simplistic direct cache of 256 bytes arranged as 16 cache lines of 16 bytes each. Assume that the low order 4 bits of an address indicates the byte within the cache line and the next 4 bits indicate which cache line slot should be used. Assuming no useful data is in the cache at the beginning, how many cache misses will result from the following sequence of addresses being read from memory. Note each cache line that will be loaded into the cache in order. Show the state of the cache at the end of this activity. (each address is given in hexadecimal)

1. cache behavior Consider an overly simplistic direct cache of 256 bytes arranged as 16 cache lines of 16 bytes each. Assume that the low order 4 bits of an address indicates the byte within the cache line and the next 4 bits indicate which cache line slot should be used. Assuming no useful data is in the cache at the beginning, how many cache misses will result from the following sequence of addresses being read from memory. Note each cache line that will be loaded into the cache in order. Show the state of the cache at the end of this activity. (each address is given in hexadecimal)

Computer Networking: A Top-Down Approach (7th Edition)

7th Edition

ISBN:9780133594140

Author:James Kurose, Keith Ross

Publisher:James Kurose, Keith Ross

Chapter1: Computer Networks And The Internet

Section: Chapter Questions

Problem R1RQ: What is the difference between a host and an end system? List several different types of end...

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Question

1. cache behavior
Consider an overly simplistic direct cache of 256 bytes arranged as 16 cache
lines of 16 bytes each. Assume that the low order 4 bits of an address indicates
the byte within the cache line and the next 4 bits indicate which cache line slot
should be used.
Assuming no useful data is in the cache at the beginning, how many cache
misses will result from the following sequence of addresses being read from
memory. Note each cache line that will be loaded into the cache in order.
Show the state of the cache at the end of this activity.
(each address is given in hexadecimal)
00A20140 Miss
00A20144 Hit
7FFF2120 Miss
7FFF211C Miss
7FFF2108
00A20100
7EFF2100
7FFF10F8
7EFF10E0
7EFF10F0
00A20160
00A20164
00A20160
00A20108
00A20140

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