1. cache behavior Consider an overly simplistic direct cache of 256 bytes arranged as 16 cache lines of 16 bytes each. Assume that the low order 4 bits of an address indicates the byte within the cache line and the next 4 bits indicate which cache line slot should be used. Assuming no useful data is in the cache at the beginning, how many cache misses will result from the following sequence of addresses being read from memory. Note each cache line that will be loaded into the cache in order.

1. cache behavior Consider an overly simplistic direct cache of 256 bytes arranged as 16 cache lines of 16 bytes each. Assume that the low order 4 bits of an address indicates the byte within the cache line and the next 4 bits indicate which cache line slot should be used. Assuming no useful data is in the cache at the beginning, how many cache misses will result from the following sequence of addresses being read from memory. Note each cache line that will be loaded into the cache in order.

Computer Networking: A Top-Down Approach (7th Edition)

7th Edition

ISBN:9780133594140

Author:James Kurose, Keith Ross

Publisher:James Kurose, Keith Ross

Chapter1: Computer Networks And The Internet

Section: Chapter Questions

Problem R1RQ: What is the difference between a host and an end system? List several different types of end...

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