has a cách è with block size 64 bytes. The main memory has k banks, each bank being c bytes wide. Consecutive c-byte chunks are mapped on consecutive banks with warp-around. All the k banks can be accessed in parallel, but two accesses to the same bank must be serialized. A cache block access may involve multiple iterations of parallel bank accesses depending on the amount of data obtained by accessing all the k banks in parallel. Each iteration requires decoding the bank numbers to be accessed in parallel and this takes k/2 ns. The latency of one bank access is 80 ns. Ifc=2 and k=24, then latency of retrieving a cache block starting at address zero from main memory is
has a cách è with block size 64 bytes. The main memory has k banks, each bank being c bytes wide. Consecutive c-byte chunks are mapped on consecutive banks with warp-around. All the k banks can be accessed in parallel, but two accesses to the same bank must be serialized. A cache block access may involve multiple iterations of parallel bank accesses depending on the amount of data obtained by accessing all the k banks in parallel. Each iteration requires decoding the bank numbers to be accessed in parallel and this takes k/2 ns. The latency of one bank access is 80 ns. Ifc=2 and k=24, then latency of retrieving a cache block starting at address zero from main memory is
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Transcribed Image Text:A CPU has a cache with block size 64 bytes. The
main memory has k banks, each bank being cbytes
wide. Consecutive c-byte chunks are mapped on
consecutive banks with warp-around. All thek banks
can be accessed in parallel, but two accesses to the
same bank must be serialized. A cache block access
may involve multiple iterations of parallel bank
accesses depending on the amount of data obtained
by accessing all the k banks in parallel. Each iteration
requires decoding the bank numbers to be accessed
in parallel and this takes k/2 ns. The latency of one
bank access is 80 ns. Ifc=2 and k=24, then latency
of retrieving a cache block starting at address zero
from main memory is
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