Design a machine with a byte addressable main memory of 2 bytes and and block size of 8 bytes. Assume that a direct mapping cache memory consisting of 32 lines is used with this machine. a-Show the format of cache memory addresses. b-Find tag, block and word for the address (0001 0001 0001 1011) using đirect mapping.

Design a machine with a byte addressable main memory of 2 bytes and and block size of 8 bytes. Assume that a direct mapping cache memory consisting of 32 lines is used with this machine. a-Show the format of cache memory addresses. b-Find tag, block and word for the address (0001 0001 0001 1011) using đirect mapping.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter6: System Integration And Performance

Section: Chapter Questions

Problem 22VE

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For a direct-mapped cache design with 64-bit addresses, the following bits of the address are used to access the cache: Tag Index Offset 63-13 12-4 3-0 a. What is the cache block size (in bytes)?b. What is the cache size (in bytes)?c. What is the total number of bits (including valid bit, tag bits and data array bits) to implement this cache?d. For the same block and cache sizes, you want to implement a 4-way set-associative cache, what is the number of index bit and the number of tag bits?
Suppose a byte-addressable computer using set-associative cache has 216 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes.Q.) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache; that is, what are the sizes of the tag, set, and offset fields?
3. The table below represents five lines from a cache that uses fully associative mapping with a block size of 8. Identify the address of the shaded data, 0xE6, first in binary and then in hexadecimal. The tag numbers and word id bits are in binary, but the content of the cache (the data) is in hexadecimal. Word id bits Tag 000 001 010 011 100 101 110 111 ------------------------------------------ 1011010 10 65 BA 0F C4 19 6E C3 1100101 21 76 CB 80 D5 2A 7F B5 0011011 32 87 DC 91 E6 3B F0 A6 1100000 43 98 ED A2 F7 4C E1 97 1111100 54 9A FE B3 08 5D D2 88
.2: Below is a list of 32-bit memory address references, given as word addresses. 3, 180, 43, 2, 191, 88, 253 For each of these references, identify the binary address, the tag, and the index given a direct- mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 2-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 4-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty.
Suppose a computer using direct mapped cache has 232 byte of byte-addressable main memory, and a cache of 1024 blocks, where each cache block contains 32 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag, block, and offset fields? c) To which cache block will the memory address 0x000063FA map?
Suppose a computer using direct mapped cache has 2^24 bytes of byte- addressable main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. (Note: 64K = 26 * 210) a) How many blocks of main memory are there? b) What is the format of a memory address as seen by cache, i.e., what are the sizes of the tag, block, and offset fields?
A digital computer has a memory unit of 64K X 16 and a cache memory of 1K words. The cache uses direct mapping with a block size of four words.i) How many bits are there in the tag, index, block and word fields of the address format?ii) How many bits are there in each word of cache, and how are they divided into functions? Include a valid bit.iii) How many blocks can the cache accommodate?
A computer of 32 bits has a cache memory of 64 KB with a cache line size of 64 bytes. The cache access time is 20 ns, and the miss penalty is 120 ns. The cache is 2-way associative. a) What is the number of cache lines? b) What is the number of cache sets? c) What is the number of lines per set? d) Draw a scheme of this cache. e) Calculate the time to read a word in case of miss.
Cache Mapping a. A computer system has a main memory with 128 blocks and a cache with 32 blocks. If it uses direct mapping, how many main memory blocks can be mapped to a single cache block? b. In a set-associative cache with 64 blocks and divided into 4 sets, determine the associativity of each set. c. For a fully associative cache with 256 blocks, how many sets are there?
d. Find out tag-set-word bits for memory address: 24EA09CHfor two-way set associative (Assume cache memory size 64 KB, number of bytes in each line is 8 bytes, and memory size is 64MB).
ALSO: What is the hit ratio for the memory accesses (Round to the nearest percent.)
1)Encode the binary data 1010101010 into an even parity Hamming code. 2)A direct mapped cache consists of 256 slots. Main memory contains 64K blocks of 16 words each. Access time of the cache is 15 ns, and that for the main memory is 120 ns. Assume that main memory is accessed in parallel with cache look up. Initially, the cache is empty. (a) Give the format of the memory address. (b) Compute the effective access time, if suppose the hit ratio for read is 90%.