1- Show how to build each of the following logic functions using one or more74x138 binary decoders and NAND gates.(Hint: Each realization should be equivalent to a sum of minterms.)a)b)(a) F=Σx,y,z(2,5,7)(b) F=ПA,B,C (2,4,5,6,7)2- Show how to build all four of the following functions using one 3-to-8 decoderwith active-low outputs and four 2-input NAND gates:..F1 X' Y' Z' + X · Y · Z'..F3=X' Y. Z' + X. Y'. Z..F2 = X' Y'. Z+X' · Y · Z'..F4=X. Y'. Z' + X' · Y · Z3- Design a gate-level circuit 10-to-4 encoder with inputs in the 1-out-of-10 code and outputs ina code like normal BCD.

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Answered: 1- Show how to build each of the…

Electric Motor Control

10th Edition

ISBN:9781133702818

Author:Herman

Publisher:Herman

Chapter22: Sequence Control

Section: Chapter Questions

Problem 6SQ: Draw a symbol for a solid-state logic element AND.

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T: Answer thne f. questions: 1) The hexadecimal number ´Al' has the decimal value equivalent to (A) 80 (B) 161 (C) 100 (D) 101 2) The output of a logic gate is 0 when all its inputs are logic 1. The logic is either (A) a NAND or an EX-OR (B) an OR or an EX-NOR (C) an AND or an EX-OR (D) an NOR or an EX-NOR 3) The Gray code of the Binary number 1100111 is (A) 1011011 (B) 1010100 (C) 1001001 (D) 101101 4) When simplified with Boollean Algebra (a+b)(a+c) simplifies to (A) a (B) a+a(b+c) (C) a(1+bc) (D) a+bc 5) -31 is represented as a sign Binary number ( using Sign-magnitude form ) equal to (A) 00011111 (B) 10101001 (C) 01110010 (D) 00101101 6) The Binary number 110111 is equivalent to decimal number (A) 25 (B) 55 (C) 26 (D) 34 7) With 4 bit, what the range of decimal values if the number is 2's complement signed number. (A) -32 to +31 (B) -2 to +1 (C) -8 to +7 (D) None of these
need help with digital logic
Below is an example of an NMOS logic circuit. For all of the MOSFETs in the circuit below, assume V = 1 V and k = 50 mA/V². th W R₂ = 5600 PEETHIPPIN R₁ - 4700 M3 M₁ M. 0 a. Indicate and verify the state of each MOSFET and V for the following input combinations. Fill-out the table below for each assumed state of the MOSFET for every input combination. Use R approximation for linear operation and three significant ds(on) figures for the voltages. 오 Ao SV why
3. Discussion: 1. Convert the gray code 01011001 to decimal number and show your work. 2. Convert the gray code 00101101 to binary number and show your work. 3. Design a 8-bit binary to gray code conversion circuit using logic gates and verify your design. 4. Design a 8-bit gray to binary code conversion circuit using logic gates and verify your design.
4. a. Design a Combinational circuit with three inputs, (A, B, and C) and four outputs, (U, V, W, and X) with the 2- i/p NOR gate only for the following logic. When the decimal value of the input is 4, 5, 6, or 7 the binary output is one less than the input (input-1). When the decimal value of input is 0, 1, 2, or 3, the output is two greater than (input +2) the input. b. A majority circuit is a combinational circuit whose output is equal to 1 if the input variables have more no. of 1's than 0's. The output is 0 otherwise. Design Using Boolean laws, three input Majority circuits with P, Q, and R as input, output Function T and its complement, Prove.
Design counter that counts from 00 to 59, using the IC 74LS90 ripple counter and use two 7 segment display to display the result count. You can also use 7447 binary to 7-segment Display Decoder in logicworks.
Using a MINIMUM number of Symbolic Logic gates and IC chips make the following set of circuits in this pattern: Gated SR Latch 3 inputs NAND Symbolic NAND IC Output Output S'R' Latch (BE CAREFUL OF INITIAL CONDITIONS -- SEE WHICH CAUSES RACE CONDITION!) 2 inputs NAND Symbolic NAND IC Output Output Gated D Latch 2 inputs Inverter, NAND Symbolic NAND Symbolic NAND IC Output Output Output The details... INTERACTIVE INPUT:Use only the number of Interactive Input buttons specified and put them at the far left. EVERY CIRCUIT to the right of the buttons will use these for input. NAND Symbolic Circuit:Using only the symbolic NAND gates…
Design the following combinational logic circuit with a four-bit input and a three-bit output. The input represents two unsigned 2-bit numbers: A1 A0 and B1 B0. The output C2 C1.C0 is the result of the integer binary division A1 A0/B1 B0 rounded down to three bits. The 3-bit output has a 2-bit unsigned whole part C2 C1 and a fraction part CO. The weight of the fraction bit CO is 21. Note the quotient should be rounded down, i.e. the division 01/11 should give the outputs 00.0 (1/3 rounded down to 0) not 00.1 (1/3 rounded up to 0.5). A result of infinity should be represented as 11.1. A minimal logic implementation is not required. (Hint: start by producing a truth table of your design).
Answer the D, E and F part
The waveforms in Figure 08 are applied to the 4-bit parity logic. Determine the output wave-form in proper relation to the inputs. For how many bit times does even parity occur, and how is it indicated? The timing diagram includes eight bit times. Q.21 Bit time Ao A1 A2 A3 FIGURE 08
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