Figure P7.62 shows the high−frequency equivalent circuit of an FET, including a source resistance r s . (a) Derive an expression for the low− frequency current gain A i = I o / I i . (b) Assuming R i is very large, derive an expression for the current gain transfer function A i = I o ( s ) / I i ( s ) . (c) How does the magnitude of the current gain behave as r s increases? Figure P7.62
Figure P7.62 shows the high−frequency equivalent circuit of an FET, including a source resistance r s . (a) Derive an expression for the low− frequency current gain A i = I o / I i . (b) Assuming R i is very large, derive an expression for the current gain transfer function A i = I o ( s ) / I i ( s ) . (c) How does the magnitude of the current gain behave as r s increases? Figure P7.62
Solution Summary: The author explains the low frequency current gain of the circuit by open circuiting the capacitor branch.
Figure P7.62 shows the high−frequency equivalent circuit of an FET, including a source resistance
r
s
. (a) Derive an expression for the low− frequency current gain
A
i
=
I
o
/
I
i
. (b) Assuming
R
i
is very large, derive an expression for the current gain transfer function
A
i
=
I
o
(
s
)
/
I
i
(
s
)
. (c) How does the magnitude of the current gain behave as
r
s
increases?
Find the operating point and the load line of a voltage-divider JFET biasing circuit
using the following parameters: VGS(0) = -1.3 and Vcc = 15 volts. Assume
ipss = 20 mA, RG₁ = RG2 = 10 kn, RD = 300, and Rs = 1 kn. Use Fig. 4b for
the IV characteristic of the JFET.
20nA
GS=-1.3 GS
10nA-
50
100
150
200
ID(J1)
UDS
Fig. 4b. The IV characteristics of an n-channel JFET (J113). The plots are for VGs increments of
0.05 volts. VGS(0) -1.3. The yellow and blue load lines are for examples 2 &3,
respectively.
Design the JFET circuit for the largest in swing. Use the self-bias circuit shown in
Fig. 6. Assume that VGS (0) = -1.3 and Vcc = 15 volts. Furthermore, assume that
ipss = 20 mA. Using Fig. 4b, draw the load line and identify the Q point. Explain
why this will allow the largest swing. Use ip = ipss (1-
VGS
VGS(0)
to show what
happens to i, and vps when you have a swing of 0.2 volts in vcs form its operating
point (that is, change vas by ±0.2 volts and compute the corresponding
iD and VDs).
RD
RG
Rs
0
20nA
GS=-1.3 VGS
12
10nA
-0-
Fig. 6. Circuit for Examples 2 &3.
BA-C
50
100
150
200
□ ID(J1)
UDS
Fig. 4b. The IV characteristics of an n-channel JFET (J113). The plots are for VGs increments of
0.05 volts. VGS(0) -1.3. The yellow and blue load lines are for examples 2 &3,
respectively.
please do the correct VI chrastaristics curve on excel. I am not sure if mine is correct
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