Problem 3: If we assume a CPU can process 100000 Instruction/sec. Compute the CPU utilization in the following scenarios (program 1000 instructions in average): a) Program instructions are stored in the main memory with access speed 1000 Instruction/sec. b) Program instructions are stored in the cache memory with access speed 50000 Instruction/sec.

Problem 3: If we assume a CPU can process 100000 Instruction/sec. Compute the CPU utilization in the following scenarios (program 1000 instructions in average): a) Program instructions are stored in the main memory with access speed 1000 Instruction/sec. b) Program instructions are stored in the cache memory with access speed 50000 Instruction/sec.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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8 A computer consists of a processor and an I/O device D connected to main memory M via a shared bus with a data bus width of one word. The processor can execute a maximum of 106 instructions per second. An average instruction requires five ma- chine cycles, three of which use the memory bus. A memory read or write operation uses one machine cycle. Suppose that the processor is continuously executing "background" programs that require 95% of its instruction execution rate but not any I/O instructions. Assume that one processor cycle equals one bus cycle. Now suppose the I/O device is to be used to transfer very large blocks of data between M and D. a. If programmed I/O is used and each one-word I/O transfer requires the processor to execute two instructions, estimate the maximum I/O data-transfer rate, in words per second, possible through D. b. Estimate the same rate if DMA is used.
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For the same instruction being executed: add $s1, $s2, $t0 using the following delays for each block/action: Decode + Register File Read Data Memory Access Instruction Register Read ALU (all Register Mux Memory Access operations) Write 25 200 |125 150 300 25 10 But, now assume that all types of instructions have to be executed in one clock cycle, not just the 'add' instruction. What is the minimum clock cycle from the times below which will suffice as the clock cycle time to run the microprocessor at? Choose the best answer. 845 535 545 835
6. Assume you have an instruction cache miss rate of 2%, and a data cache miss rate of 6%. The miss penalty is 100 cycles. You have a program that is 30% load-store instructions, with a base CPI of 1. What will its CPI be including cache misses?
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3. i and ii no handwriting, please
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Problem 4. There are two levels L1 and L2 of caches. L1 has hit rate 95%, and L2 has hit rate 80%. L1 has I cycle to access. L2 has 20 cycles to access. Memory has 400 cycles to access. Ignoring memory access clocks per instruction (CPI) has 1 cycle. Assume that 40% instruction has data access. Compute the CPI that includes memory access. You need to consider that there is a memory access to fetch each instruction.
Task-1: Suppose the hypothetical processor of (Fig 1.3) also has two I/O instructions:0011 Load AC from I/O0111 Store AC to I/OIn these cases, the 12-bit address identifies a particular external device. Show the program execution (Fig 1.4) for the following program:1. Load AC from device 5.2. Add contents of memory location 940.3. Store AC to device 6.Assume that the next value retrieved from device 5 is 3 and that location 940 contains a value of 2.
We will explore the impact of cache capacity on performance, focusing exclusively on the data cache and excluding instruction storage in the caches. Cache access time is directly linked to its capacity. For the sake of simplicity, let's assume that accessing the main memory takes 100ns, and in a specific program, 50% of instructions involve data access. Two distinct processors, denoted as P1 and P2, are engaged in executing this program. Each processor is equipped with its own L1 cache. L1 size L1 Miss Rate L1 Hit Time P1 64 KB 3.6% 1.26 ns P2 128 KB 3.1% 2.17ns (a) What is the AMAT for P1 and P2 assuming no other levels of cache?
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Computer Science Edit question Consider a single core processor with separate L1 instruction and data cache, unified L2 cache and cache L3, with the following penalties for misses. L1-I and L1-D misses: 5 cycles. misses on L2: 10 cycles. misses in L3: 50 cycles. The processor base CPI considering 0% misses in all caches is 1. On this processor it was run a program that has 10% memory access instructions. Consider that the miss rates are the following. L1-I: 10%, L1-D: 30%, L2: 10%, L3: 5%. Which is the system CPI?