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We want to design and measure the performance of a new processor (CPU) with 32 GPRs, 32-bit data and 16-bit address busses. a) Draw the internal organization of this CPU by showing the widths of all registers as well as all external and internal buses. Given the following assembly program: load R1, #100 load ; load constant value #100 in R1 ; load content of Memory at address 2000 into R2 R2, M [2000] R5, R2, R1 R10,#4, R5 ; add R2 to R1 and put result in R5 ; multiply R5 by 4 and put result in R10 store M[4000], R10 ; move (copy) content of R10 into Memory at addr. 4000 add mul b) How many bits would each instruction require to be encoded in binary? c) For every instruction in the above program, provide a possible binary encoding. d) Calculate the total memory (in bytes) needed to store the program. e) For every instruction in the above program, draw in a flow chart the micro execution steps. f) Assuming an execution on a 2 GHz CPU, where every step requires a number of clock cycles (cc) as shown below, calculate the execution time (in ns) for every instruction, then for the whole program. Internal Register Transfers PC Increment Decoding Memory Access Addition Multiplication 1 cc 2 cc 1 cc 10 cc 3 cc 5 cc

We want to design and measure the performance of a new processor (CPU) with 32 GPRs, 32-bit data and 16-bit address busses. a) Draw the internal organization of this CPU by showing the widths of all registers as well as all external and internal buses. Given the following assembly program: load R1, #100 load ; load constant value #100 in R1 ; load content of Memory at address 2000 into R2 R2, M [2000] R5, R2, R1 R10,#4, R5 ; add R2 to R1 and put result in R5 ; multiply R5 by 4 and put result in R10 store M[4000], R10 ; move (copy) content of R10 into Memory at addr. 4000 add mul b) How many bits would each instruction require to be encoded in binary? c) For every instruction in the above program, provide a possible binary encoding. d) Calculate the total memory (in bytes) needed to store the program. e) For every instruction in the above program, draw in a flow chart the micro execution steps. f) Assuming an execution on a 2 GHz CPU, where every step requires a number of clock cycles (cc) as shown below, calculate the execution time (in ns) for every instruction, then for the whole program. Internal Register Transfers PC Increment Decoding Memory Access Addition Multiplication 1 cc 2 cc 1 cc 10 cc 3 cc 5 cc

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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We want to design and measure the performance of a new processor (CPU) with 32 GPRs, 32-bit data and 16-bit address busses. a) Draw the internal organization of this CPU by showing the widths of all registers as well as all external and internal buses. Given the following assembly program: load load add mul e) f) R1, #100 R2, M [2000] R5, R2, R1 R10, #4, R5 store M [4000], R10 ; load constant value #100 in R1 ; load content of Memory at address 2000 into R2 ; add R2 to R1 and put result in R5 ; multiply R5 by 4 and put result in R10 ; move (copy) content of R10 into Memory at addr. 4000 b) How many bits would each instruction require to be encoded in binary? c) For every instruction in the above program, provide a possible binary encoding. d) Calculate the total memory (in bytes) needed to store the program. For every instruction in the above program, draw in a flow chart the micro execution steps. Assuming an execution on a 2 GHz CPU, where every step requires a number of clock cycles (cc) as shown below, calculate the execution time (in ns) for every instruction, then for the whole program. Internal Register Transfers PC Increment Decoding Memory Access Addition Multiplication 1 cc 2 cc 1 cc 10 cc 3 cc 5 cc
Transcribed Image Text:We want to design and measure the performance of a new processor (CPU) with 32 GPRs, 32-bit data and 16-bit address busses. a) Draw the internal organization of this CPU by showing the widths of all registers as well as all external and internal buses. Given the following assembly program: load load add mul e) f) R1, #100 R2, M [2000] R5, R2, R1 R10, #4, R5 store M [4000], R10 ; load constant value #100 in R1 ; load content of Memory at address 2000 into R2 ; add R2 to R1 and put result in R5 ; multiply R5 by 4 and put result in R10 ; move (copy) content of R10 into Memory at addr. 4000 b) How many bits would each instruction require to be encoded in binary? c) For every instruction in the above program, provide a possible binary encoding. d) Calculate the total memory (in bytes) needed to store the program. For every instruction in the above program, draw in a flow chart the micro execution steps. Assuming an execution on a 2 GHz CPU, where every step requires a number of clock cycles (cc) as shown below, calculate the execution time (in ns) for every instruction, then for the whole program. Internal Register Transfers PC Increment Decoding Memory Access Addition Multiplication 1 cc 2 cc 1 cc 10 cc 3 cc 5 cc
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