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Problem 4. There are two levels L1 and L2 of caches. L1 has hit rate 95%, and L2 has hit rate 80%. L1 has I cycle to access. L2 has 20 cycles to access. Memory has 400 cycles to access. Ignoring memory acces, clocks per instruction (CPI) has 1 cycle. Assume that 40% instruction has data access. Compute the CPI that includes memory access. You need to considen that there is a memory access to fetch each instruction.

Problem 4. There are two levels L1 and L2 of caches. L1 has hit rate 95%, and L2 has hit rate 80%. L1 has I cycle to access. L2 has 20 cycles to access. Memory has 400 cycles to access. Ignoring memory acces, clocks per instruction (CPI) has 1 cycle. Assume that 40% instruction has data access. Compute the CPI that includes memory access. You need to considen that there is a memory access to fetch each instruction.

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Problem 4. There are two levels L1 and L2 of caches. L1 has hit rate 95%, and L2 has hit rate 80%. L1 has I cycle to access. L2 has 20 cycles to access. Memory has 400 cycles to access. Ignoring memory access clocks per instruction (CPI) has 1 cycle. Assume that 40% instruction has data access. Compute the CPI that includes memory access. You need to consider that there is a memory access to fetch each instruction.
Transcribed Image Text:Problem 4. There are two levels L1 and L2 of caches. L1 has hit rate 95%, and L2 has hit rate 80%. L1 has I cycle to access. L2 has 20 cycles to access. Memory has 400 cycles to access. Ignoring memory access clocks per instruction (CPI) has 1 cycle. Assume that 40% instruction has data access. Compute the CPI that includes memory access. You need to consider that there is a memory access to fetch each instruction.
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