Problem Complete the following table, filling in the state transitions specifically for Processor 1, block A. Assume a cache with a write-back policy (cache can hold only one block at a time) which is initially empty. Include the new state of block A in Processor 1 only after each event, and note any external actions taken by Processor 1. Assume that these accesses occur in order, and that no other traffic occurs at the same time. Here, ESI refers to the standard snoopy protocol in Figure 5.7 (page 361), whereas MESI is the modified snoopy protocol in the lecture slide which uses an additional state. Please note that M (modified) state in MESI is in fact similar to the E (exclusive) state in ESI, and E (exclusive) state in MESI is an additional (read/only) state. To avoid this confusion, some literature uses the term MSI to refer to ESI protocol.

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
icon
Related questions
Question

"Figure 5.7" in the statement is show below. This picture is from Computer Architecture: A Quantitive Approach

Write-back block
Write miss
for block
CPU write hit
CPU read hit
Invalid
Place write miss on bus
CPU write
Write miss for this block
Invalidate for this block
Exclusive
(read/write)
CPU read
Place read miss on bus
CPU read miss
Write-back data; place read miss on bus
CPU write
Read miss for block Write-back block
Place invalidate on bus
CPU write miss
CPU write miss
Place write miss on bus
Write-back data
Place write miss on bus
CPU
read
hit
Shared
(read only)
CPU
read
miss
Place read
miss on bus
Figure 5.7 Cache coherence state diagram with the state transitions induced by the
local processor shown in black and by the bus activities shown in gray. As in
Figure 5.6, the activities on a transition are shown in bold.
Transcribed Image Text:Write-back block Write miss for block CPU write hit CPU read hit Invalid Place write miss on bus CPU write Write miss for this block Invalidate for this block Exclusive (read/write) CPU read Place read miss on bus CPU read miss Write-back data; place read miss on bus CPU write Read miss for block Write-back block Place invalidate on bus CPU write miss CPU write miss Place write miss on bus Write-back data Place write miss on bus CPU read hit Shared (read only) CPU read miss Place read miss on bus Figure 5.7 Cache coherence state diagram with the state transitions induced by the local processor shown in black and by the bus activities shown in gray. As in Figure 5.6, the activities on a transition are shown in bold.
Problem 2
Complete the following table, filling in the state transitions specifically
for Processor 1, block Assume a cache with a write-back policy (cache can hold only one
block at a time) which is initially empty. Include the new state of block A in Processor 1 only
after each event, and note any external actions taken by Processor 1. Assume that these accesses
occur in order, and that no other traffic occurs at the same time. Here, ESI refers to the standard
snoopy protocol in Figure 5.7 (page 361), whereas MESI is the modified snoopy protocol in the
lecture slide which uses an additional state. Please note that M (modified) state in MESI is in
fact similar to the E (exclusive) state in ESI, and E (exclusive) state in MESI is an
additional (read/only) state. To avoid this confusion, some literature uses the term MSI to refer
to ESI protocol.
Event
Local Write A
Local Read B
Bus Read A
Bus Write A
Local Write A
Local Read A
Bus Read A
Local Write A
Local Write B
Local Read A
Local Write A
Local Write B
ESI for
block A
E
MESI for
block A
M
External actions for ESI and MESI
Both send invalidations
Transcribed Image Text:Problem 2 Complete the following table, filling in the state transitions specifically for Processor 1, block Assume a cache with a write-back policy (cache can hold only one block at a time) which is initially empty. Include the new state of block A in Processor 1 only after each event, and note any external actions taken by Processor 1. Assume that these accesses occur in order, and that no other traffic occurs at the same time. Here, ESI refers to the standard snoopy protocol in Figure 5.7 (page 361), whereas MESI is the modified snoopy protocol in the lecture slide which uses an additional state. Please note that M (modified) state in MESI is in fact similar to the E (exclusive) state in ESI, and E (exclusive) state in MESI is an additional (read/only) state. To avoid this confusion, some literature uses the term MSI to refer to ESI protocol. Event Local Write A Local Read B Bus Read A Bus Write A Local Write A Local Read A Bus Read A Local Write A Local Write B Local Read A Local Write A Local Write B ESI for block A E MESI for block A M External actions for ESI and MESI Both send invalidations
Expert Solution
steps

Step by step

Solved in 5 steps with 3 images

Blurred answer
Knowledge Booster
Properties of Different Architectures
Learn more about
Need a deep-dive on the concept behind this application? Look no further. Learn more about this topic, computer-science and related others by exploring similar questions and additional content below.
Recommended textbooks for you
Database System Concepts
Database System Concepts
Computer Science
ISBN:
9780078022159
Author:
Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:
McGraw-Hill Education
Starting Out with Python (4th Edition)
Starting Out with Python (4th Edition)
Computer Science
ISBN:
9780134444321
Author:
Tony Gaddis
Publisher:
PEARSON
Digital Fundamentals (11th Edition)
Digital Fundamentals (11th Edition)
Computer Science
ISBN:
9780132737968
Author:
Thomas L. Floyd
Publisher:
PEARSON
C How to Program (8th Edition)
C How to Program (8th Edition)
Computer Science
ISBN:
9780133976892
Author:
Paul J. Deitel, Harvey Deitel
Publisher:
PEARSON
Database Systems: Design, Implementation, & Manag…
Database Systems: Design, Implementation, & Manag…
Computer Science
ISBN:
9781337627900
Author:
Carlos Coronel, Steven Morris
Publisher:
Cengage Learning
Programmable Logic Controllers
Programmable Logic Controllers
Computer Science
ISBN:
9780073373843
Author:
Frank D. Petruzella
Publisher:
McGraw-Hill Education