. Which has the lower average memory access time for both split and unified cache? Consider the below-given assumptions: Split cache: 16 KB instructions +16 KB data Unified cache: 32 KB (instructions + data). Miss penalty is 40 cycles, hit time is 1 cycle. 75% of the total memory accesses for instructions and 25% of the total memory accesses for data. On the unified cache, a load or store hit takes an extra cycle, since there is only one port for instructions and data. Use Miss rate given in below table Size Instruction Cache Data Cache Unified Cache 16 KB 0.64% 6.47% 2.87% 32 KB 0.39% 4.82% 1.99%
a. Assume data stored as 011110111, use hamming code to calculate check bits and an odd parity scheme, and also using even parity schemes. Show all your calculations and also verify with the error message 011110111.
b. Which has the lower average memory access time for both split and unified cache?
Consider the below-given assumptions:
Split cache: 16 KB instructions +16 KB data
Unified cache: 32 KB (instructions + data).
Miss penalty is 40 cycles, hit time is 1 cycle.
75% of the total memory accesses for instructions and 25% of the total memory accesses for data. On the unified cache, a load or store hit takes an extra cycle, since there is only one port for instructions and data.
Use Miss rate given in below table
|
Size |
Instruction Cache |
Data Cache |
Unified Cache |
|
16 KB |
0.64% |
6.47% |
2.87% |
|
32 KB |
0.39% |
4.82% |
1.99% |
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