C1. Consider a main memory with size 4GB with cache size 16 KB and memory block is 8 bytes.Assume that the memory word is 1 byte. Answer the following questions:a. How many address bits are required to address the main memory locations?b. How many lines are there in the cache memory?c. Determine how to split the address (s-r, r, w) for direct mapping.d. Determine how to split the address (s-d, d, w) for set associative mapping. Assume each cacheset is 2 lines of cache.

We are given main memory size as 4GB and cache as 16KB. Memory block is 8B. Each word is 1 byte . I…

Answered: C1. Consider a main memory with size…

Computer Networking: A Top-Down Approach (7th Edition)

7th Edition

ISBN:9780133594140

Author:James Kurose, Keith Ross

Publisher:James Kurose, Keith Ross

Chapter1: Computer Networks And The Internet

Section: Chapter Questions

Problem R1RQ: What is the difference between a host and an end system? List several different types of end...

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4. Assume a cache of 32 Kbytes organized as 4 K lines of 8 bytes each. The main memory is 64 MB organized logically as 8 M blocks of 8 bytes each. a. Determine how to split the address (s-r, r, w) for direct mapping. b. Determine how to split the address (s. w) for associative mapping. c. Determine how to split the address (s-d, d, w) for set associative mapping. Assume each cache set is 4 lines of cache.
In a computer with a 32-bit data-bus, how many 4-bit wide memory components are used? the answer to this part is 32/4 = 8 components (2-bit wide) I need the answer to part two, please If the size of each 4-bit memory component is 4 xn cells where n = 1G (i.e., 4 x n uniquely addressable locations-n: row, 4:2 column/width), what is the total capacity of the memory system? Show your answer in power of 2. (hint: 1000 - 210)
Create a memory mapping from the cache memory of 512 MB to the main memory of 4 GB using the four-way set associative approach with a block size of 1 MB. Consider that each memory location may be accessed using a byte address.
Question 2: Consider a memory of 64 Kbytes. It has a 2 Kbytes cache organized in a direct-mapped manner with 64 bytes per cache block. Assume that the size of each memory word is 1 byte. a) What is the length of the address provided by the processor? b) What is the number of blocks in main memory? c) How many lines does the cache have? d) Calculate the number of bits in each of the Tag, Block(SET), and Word fields (OFFSET) of the memory address.
4. Assume 32 bit memory addresses, which are byte addresses. You have a direct-mapped cache with a block size of 8 bytes, and a size of 128 blocks. How many bits will the index, block offset, and tag be? How many total bits are required for the cache, including the data?
Consider a computer system with a 32-bit logical address and 4-KB page size. The system supports up to 512MB of physical memory. How many entries are there in each of the following: a) A conventional single-level page table Consider a logical address space of 256 pages with a 4-KB page size, mapped onto a physical memory of 64 frames. a) How many bits are required in the logical address? b) How many bits are required in the physical address?
QUESTION 2 Suppose a computer using direct mapped cache is using 216 (64K) bytes of byte-addressable main memory, and a cache size of 4096 bytes, where each cache block contains 256 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by cache, i.e. what are the length of the tag, block, and offset fields? c) Given memory address 2B9D (in hexadecimal format), which block in the cache will be searched? (What is that block's id?)
Exercise 1: Consider a word-addressable memory of 16 GB, where each word is composed of 128 bits. This memory is directly mapped to a cache of 1 MB composed of blocks where each block contains 16 words. a) What is length (in bits) of the address provided by the processor? b) What is the length (in Bytes) of one memory block? c) How many lines does the cache have? d) What is the length (in bits) of each of the TAG, LINE, and OFFSET? e) Which line in cache can hold the address 00000FOF?

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