Assume a program has 20% store and load. When we run this program in a computer, we observe that L1  instruction cache has a hit rate of 98% and L1 data cache has a hit rate of 96%. The L2 cache has a hit rate of 80%.  The access time of L1 cache is 2 cycle, and the access time of L2 cache is 40 cycles. If a miss occurs in L2, we have  to go to main memory and the penalty is 100 cycles. Assume that the cache uses physical address. a) Without a TLB, what is the AMAT? b) Assume a TLB is built in the cache and its access time is ignored. If the TLB has a 99% hit rate, what is the  new AMAT? c) If there is a 0.01% chance that a page fault happens, and the penalty to fetch a page from the disk is 106 cycles, what is the new AMAT?

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