A program sees a 4% miss rate on both the Instruction Cache and the Data Cache. Every instruction requires access to the Instruction cache. Only 35% of the instructions require data access from the Data Cache. The miss penalty for either the data or the instruction cache is 100 cycles. Assume the average Clocks per Instruction (CPI) is 2 without any memory stalls (this is a hypothetical machine where if there were no misses on that instruction, it would get executed in 2 clock cycles. We are not worrying about how it is implemented, just, that suppose it was possible). Assume the number of instructions in a program is X.    F1: What is the number of 'instruction miss cycles'? (The number of clock cycles lost due to a miss on the Instruction Cache) F2: What is the number of 'data miss cycles'? F3: What is the total run time of the program including the missed cycles dues to data and instruction misses? F4: What is the ratio of the actual run time (from question F3 above) to the fictitious run time if there were no cache misses at all?

Q: For the instruction being executed: add $s1, $s2, $t0 use the following delays for each…

A: Explanation: First, read the registers. and, Instruction access memory. and, Decode and register…

Q: For a computer's instruction set to be orthogonal, it must be able to generate a "backup"…

A: A computer's instruction set is a collection of machine language instructions that the processor can…

Q: 4 Consider a microprocessor that has a block I/O transfer instruction such as that found on the…

A:

Q: , 25% reads and 10% writes, and every other instruction type is 1 cycle. You have a 2-way set…

A: since addresses size supported by the hardware's is 40bit's total size of the main memory is 240…

Q: Assume the miss rate of an instruction cache is 4% and the miss rate of the data cache is 5%. If a…

A: Given the following facts, calculate how much faster a processor would run with a perfect cache that…

Q: Assume the miss rate of an instruction cache is 2% and the miss rate of the data cache is 4%. If a…

A: GIVEN: Instruction miss rate= 2% Data miss rate= 4% CPI without memory stalls =2 Miss penalty= 100…

Q: SET reg, immed; 3 clock cycles LOAD reg, mem ; 4 clock cycles ADD reg, reg; 3 clock cycles ADD reg,…

A: The answer is

Q: onsider a multilevel computer in which levels are vertically stacked, with the lowest level being…

A: Answer :

Q: In this case, every instruction gets its own data in a way that is completely separate from how the…

A: Single Instruction Multiple Data (SIMD) seems to be the sort of computer architecture referred to in…

Q: Consider a microprocessor that has a block I/O transfer instruction such as that found on the Z8000.…

A: As per guidelines I can answer only first question. Thank You. Given data:               Its first…

Q: Suppose a computer uses a Load-Store Instruction Set Architecture with 32-bit instructions and 64…

A: An instruction set is a collection of operations that a computer's central processing unit (CPU) can…

Fundamentals of Input and Output Performance

The I/O subsystem is a component of computer system design that uses buses to assist communication between the Central Processing Unit, Computer Memory/Storage, and Input and Output Devices (that is known as peripheral devices). The I/O subsystem includes disc controllers, tape drives, discs, system buses, and other devices. The I/O database application reads and writes drives using the operating system windows I/O.