, 25% reads and 10% writes, and every other instruction type is 1 cycle. You have a 2-way set associative, write-back cache with 64 bytes in each cache line. Write back is handled by hardware and does not involve any delays. Memory latency is 30 cycles, bandwidth is 8 bytes per cycle. You can choose between: A. 256KB cache with access cost of 1 cycle to read a word into a register, and a miss rate of 15% o B. 1MB cache with a miss rate of 5% but aaccess cost of 2 cycles for every transfer between a register and cache. For each configuration of cache, calculate: size of tag for a cache line, and
Assume we have a machine with 64 bit (8 byte) word size and 40 bit maximum memry address limited by the hardware. This machine has a 3 GHz clock. All instructions take 1 cycle except for floating point which takes 2 cycles, and memory instructions. It has an L1 cache but no L2 or other levels.
Assume the instruction mix is 5% floating point, 25% reads and 10% writes, and every other instruction type is 1 cycle.
You have a 2-way set associative, write-back cache with 64 bytes in each cache line. Write back is handled by hardware and does not involve any delays. Memory latency is 30 cycles, bandwidth is 8 bytes per cycle.
You can choose between:
A. 256KB cache with access cost of 1 cycle to read a word into a register, and a miss rate of 15% o
B. 1MB cache with a miss rate of 5% but aaccess cost of 2 cycles for every transfer between a register and cache.
For each configuration of cache, calculate: size of tag for a cache line, and size of cache addresses (both sizes in number of bits)
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