Given the following table:Program XInstruction Count = 29 x 10³Program YInstruction Count = 18 x 105Processor 1Clock Rate = 3.3GHZExecution Time12msExecution Time9msTable 1.0Processor 2Clock Rate = 2.8GHZExecution Time(b) Calculate the CPI rate for Program X on BOTH processors.16msExecution TimeAnswer the following questions based on the information above.*You are required to indicate all working steps and marks will be given accordingly.(c) Calculate the MIPS rate for BOTH programs on BOTH processors.7ms(d) Using Program Y as a benchmark, determine which processor is faster and by howmuch.

Introduction In computer and software engineering, execution refers to the procedure by which a…

Answered: Given the following table: Program X…

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Q2. For the following assume that values A, B, C, D, E, and F reside in memory. Also assume that instruction operation codes are represented in 6 bits, memory addresses are 64 bits, data size is 32 bits and register addresses are 5 bits. a. For each instruction set architecture shown in Figure A.1, how many addresses or names (including both memory and register), appear in each instruction for the code to compute C = A+ B, and what is the total code size? passor TOS Memory (A) Accumulator (C) Registry (D) Re loed oore Figure A.1 Operand locations for four instruction set architecture classes. The arrows indicate whether the oper and is an input or the result of the orithmetic-logical unit ALU operation, or both an input and result Lighter shoes indicate inputs, and the dark shode indicates the result in a top of stack (TOS) register points to the top input operand, which is combined with the operand below. The first operand is removed from the stack, the result takes the place of the…
Assume that the operation times of one add instruction for the major functional units are 325 ps for memory access, 185 ps for ALU operations and 125 ps for register file read/writes. Please fill the table first and perform the following a )What is the total cycle in single-cycle implementation? b )What is the total cycle in pipelining implementation? c) What is the total cycle in pipelining implementation if there are 5 million add instructions? d) What is the total cycle in pipelining implementation for 5 million add instructions, if the stages are balanced? e)What is the speed up of pipelining implementation over single-cycle implementation?
Program X Instruction Count = 29 x 105 Program Y Instruction Count = 18 x 105 Processor 1 Clock Rate = 3.3GHZ Execution Time 12ms Execution Time 9ms Table 1.0 Processor 2 Clock Rate = 2.8GHZ Execution Time 16ms Execution Time 7ms Answer the following questions based on the information above. *You are required to indicate all working steps and marks will be given accordingly. (a) Calculate the instruction execution rate for BOTH processors when running BOTH programs.
H.W.: Consider a hypothetical machine with two steps instruction cycle: fetch cycle and execute cycle. The characteristics of the machine is given in Figure 8 with the following explanation: The processor contains a single data register, called an accumulator (AC). • Both instructions and data are 8 bits long. • The memory is organized using 8-bit words. • The instruction format provides 2 bits for the opcode, and up to 26 = 64 words of memory can be directly addressed. Opcode Address (a) Instruction format Magnitude (b) Integer format Program counter (PC)= Address of instruction Instruction register (IR)- Instruction being executed Accumulator (AC) Temporary storage (c) Internal CPU registers -Load AC from memory Store AC to memory - Add to AC from memory (d) Partial list of opcodes Figure 8 Characteristics of a Hypothetical Machine Figure 9 illustrates a partial program execution, showing the relevant portions of memory and processor registers after the first instruction, 64H has…
ISA of a hypothetical CPU 1 Address Memory: Address Data - (8-bits) LOAD M 100 25 STORE M 101 90 ADD M 102 65 SUB M 103 36 MUL M 104 22 105 77 DIV M 106 89 Where: Note: all numbers are hexadecimal M-a memory address AC - accumulator Sample program: //line 1 /line 2 //line 3 //line 4 //line 5 //line 6 LOAD 100 ADD 101 STORE 106 LOAD 102 SUB 103 STORE 105 Answer the following questions based on the given information above. 1. What is the content of memory location 106 after executing line 3? 2. What is the content of memory location 105 after executing line 6? 3. Write a program segment that will multiply the content of memory location 105 with the content of AC and store the result at memory location 100. а. b. 4. For this CPU, what is the width of the program counter? (express answer in terms of bits, do not include the word "bits" in your answer)
Assume: CPU Clock = 1 GHz 1 OP requires 5 clock cycles (arithmetic instruction, conditional, etc.) 1 memory access requires 100 clock cycles (Read or Write) Problem size: N = 1,000,000 (1 million) There is no cost associated with the loop index variable: do not count any arithmetic instructions for initializing or incrementing the loop index value, do not count any memory accesses for accessing and using the loop index variable in your computation of a sum. Assume the loop index variable is "free of charge" There is no memory cost of accessing and updating your accumulator variable (e.g., sum += ...), but there is an arithmetic operation involved in updating the accumulator variable. Questions: 1. For algorithm #1 shown below (direct sum): • How many arithmetic instructions are required by this algorithm? • How many memory accesses are required by this algorithm? • How many clocks are required by this algorithm? • What is the CPI (cycles per instruction) required by this algorithm? •…
Convert the given hex value to its R-format MIPS instruction by completing the following table. The instruction and letters for registers must be in lower case. DO NOT TYPE DOLLAR SIGNS WITH REGISTERS. Hex Opcode (decimal) rs (decimal) rt (decimal) rd (decimal) funct (decimal) Instruction 02488822 O 18 16 17 34 sub s4 $$1 " $ to " LA
Consider the execution of a program that results in the execution of 8 million instructions on a 400-MHz processor. The program consists of four major types of instructions. The instruction mix and the CPI for each instruction type are given below. What is the program execution time in the second? Instruction Type Arithmetic and logic Load/store with cache hit Branch Floating-point arithmetic operation Execution Time: sec CPI 3 4 3 9 Instruction Mix (%) 60 20 12 8
Assume a 5-stage pipelined CPU (IF – ID – MU- EX – WR) requires following time for different sections: Required time 15 ns Pipeline stages Fetch Unit Decode Unit 10 ns 20 ns Memory Unit Execution Unit 8 ns 15 ns Write back Unit The maximum delay required to transfer contents from one state to another is 2ns. a) Show the time steps of pipelining stages for the first 10 instructions of a program. Assume that Instruction-4 is a conditional loop instruction. If the condition is TRUE, CPU runs instructions: 7 - 9 twice. Please note that a single-port RAM is used with the system, such that CPU read only one data from RAM or save only one data to RAM at a time. Calculate the execution time for the first 10 instructions of a program as well. b) Show the time steps and calculate the execution time for above problem while a multiport RAM is used with the system.
Suppose that we are developing a new version of the AMD Barcelona proces- sor with a 4 GHz clock rate. We have added some additional instructions to the instruction set in such a way that the number of instructions has been reduced by 15% from the values shown for each benchmark in Exercise 1.12. The execution times obtained are shown in the following table. a. Name Execution Time (seconds) Reference Time (seconds) bzip2 700 9650 SPECratio 13.7 1.13.2 [10] In general, these CPI values are larger than those obtained in previous exercises for the same benchmarks. This is due mainly to the clock rate used in both cases, 3 GHz and 4 GHz. Determine whether the increase in the CPI is similar to that of the clock rate. If they are dissimilar, why?
The Figure 1 below shows the Amdahl's law for multiprocessor (speedup vs. number of processors), where f is the fraction of code that is parallelizable. Analyse the figure below and select the statements that are TRUE: 20 f= 0.95 f = 0.90 5. f= 0.75 f= 0.5 10 100 1000 Number of Processors Figure 1. Amdahl's Low for multiprocessor Select one or more: A. Having M processors will speedup the overall system performance times M B. When f is small, the use of parallel processors has little effect C. There is much benefit of multiple processors even if the code execution is mostly serial D. As number of processors increase there are diminishing returns for using more processors dnpads
A program consists of 100,000 instructions as follows: Integer arithmetic Data transfer Floating-point arithmetic Control transfer Instruction Type M1 - 400 MHz M2 - 800 MHz Processor Type of Instruction, IC, and CPI Instruction Count decimal places) 45,000 decimal places) 36,000 10,000 9,000 Execution Time Determine the program execution time, the effective CPI for the machine, and the MIPS rate for the following processors. (each box is 2 points except CPI) seconds (round to 5 4 seconds (round to 5 5 10 3 Cycles per Instruction Type of instruction, IC, and CPI CPI (round to 2 decimal places) MIPS rate (Whole number only with round up) (Whole number only with round up)

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