Given the following table:Program XInstruction Count = 29 x 10³Program YInstruction Count = 18 x 105Processor 1Clock Rate = 3.3GHZExecution Time12msExecution Time9msTable 1.0Processor 2Clock Rate = 2.8GHZExecution Time(b) Calculate the CPI rate for Program X on BOTH processors.16msExecution TimeAnswer the following questions based on the information above.*You are required to indicate all working steps and marks will be given accordingly.(c) Calculate the MIPS rate for BOTH programs on BOTH processors.7ms(d) Using Program Y as a benchmark, determine which processor is faster and by howmuch.

Introduction In computer and software engineering, execution refers to the procedure by which a…

Answered: Given the following table: Program X…

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Program X Instruction Count = 29 x 105 Program Y Instruction Count = 18 x 105 Processor 1 Clock Rate = 3.3GHZ Execution Time 12ms Execution Time 9ms Table 1.0 Processor 2 Clock Rate = 2.8GHZ Execution Time 16ms Execution Time 7ms Answer the following questions based on the information above. *You are required to indicate all working steps and marks will be given accordingly. (a) Calculate the instruction execution rate for BOTH processors when running BOTH programs.
Assuming the same instruction mix listed in Problem 7, what is the average execution time across all instructions?
Assume: CPU Clock = 1 GHz 1 OP requires 5 clock cycles (arithmetic instruction, conditional, etc.) 1 memory access requires 100 clock cycles (Read or Write) Problem size: N = 1,000,000 (1 million) There is no cost associated with the loop index variable: do not count any arithmetic instructions for initializing or incrementing the loop index value, do not count any memory accesses for accessing and using the loop index variable in your computation of a sum. Assume the loop index variable is "free of charge" There is no memory cost of accessing and updating your accumulator variable (e.g., sum += ...), but there is an arithmetic operation involved in updating the accumulator variable. Questions: 1. For algorithm #1 shown below (direct sum): • How many arithmetic instructions are required by this algorithm? • How many memory accesses are required by this algorithm? • How many clocks are required by this algorithm? • What is the CPI (cycles per instruction) required by this algorithm? •…
what is the CPU time if the number of instructions executed by the program is 500, cycles per instruction is 5 and the clock cycle time is 200 ps ? a) 1000 secb) 50000 secc) 500000 secd) 10000 sec answer
The result for the SPEC CPU 2017 Integer Speed Result on an Intel Xeon Platinum 8490Hprocessor. This system has an enabled 120 cores, 2 chips and 2 threads/core where each benchmarkprogram is executed simultaneously on all 120 cores with the execution time and ratio for each test asshown on the table. Compute for the speed metric on base and peak.
two different processors execute same instructions, Processor one has 4Ghz clock rate and 1.5 CPI, processor two has 1.3GHz and 2.2 CPI. 1)find the processor with the highest performance expressed in instructions per second 2)if both processors execute a program in 15seconds, what is the number of cycles and instructions
Calculate the CPU execution time (expressed in milliseconds) of a program with 10 million instructions on a 2.5 GHz CPU with the following basic instruction-type breakdowns and CPIs: Arithmetic: 60%, CPI = 2 Load & Store (assuming perfect caches): 25%, CPI = 5 Branching: 15%, CPI = 3 In addition, you are told that the overall cache miss rate for instructions is 1%, the overall cache miss rate for data is 3%, and the cache miss penalty is 100 cycles. You can ignore the hit time (consider it zero).
Consider the execution of a program that results in the execution of 8 million instructions on a 400-MHz processor. The program consists of four major types of instructions. The instruction mix and the CPI for each instruction type are given below. What is the program execution time in the second? Instruction Type Arithmetic and logic Load/store with cache hit Branch Floating-point arithmetic operation Execution Time: sec CPI 3 4 3 9 Instruction Mix (%) 60 20 12 8
Assume a 5-stage pipelined CPU (IF – ID – MU- EX – WR) requires following time for different sections: Required time 15 ns Pipeline stages Fetch Unit Decode Unit 10 ns 20 ns Memory Unit Execution Unit 8 ns 15 ns Write back Unit The maximum delay required to transfer contents from one state to another is 2ns. a) Show the time steps of pipelining stages for the first 10 instructions of a program. Assume that Instruction-4 is a conditional loop instruction. If the condition is TRUE, CPU runs instructions: 7 - 9 twice. Please note that a single-port RAM is used with the system, such that CPU read only one data from RAM or save only one data to RAM at a time. Calculate the execution time for the first 10 instructions of a program as well. b) Show the time steps and calculate the execution time for above problem while a multiport RAM is used with the system.
The Figure 1 below shows the Amdahl's law for multiprocessor (speedup vs. number of processors), where f is the fraction of code that is parallelizable. Analyse the figure below and select the statements that are TRUE: 20 f= 0.95 f = 0.90 5. f= 0.75 f= 0.5 10 100 1000 Number of Processors Figure 1. Amdahl's Low for multiprocessor Select one or more: A. Having M processors will speedup the overall system performance times M B. When f is small, the use of parallel processors has little effect C. There is much benefit of multiple processors even if the code execution is mostly serial D. As number of processors increase there are diminishing returns for using more processors dnpads
If DS= 2000H and DI=200H and BX=400H and SI=1000H and the memory locations have the following data What will be the value stored in the registers after the execution of the following instructions, LDS CX, [1000] LEA SI,[DI+BX+2H] MEMORY CONTENTS Address Contents 20FFC 12 20FFD 1A 20FFE ЗВ 20FFF 74 21000 2A 21001 04 21002 8F 21003 70
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