3. Consider a pipeline in a processor that has 5 stages: (1) instruction fetch – 120 ns, (2) instruction decode - 30 ns (3) memory read - 80 ns (4) instruction execution - 30 ns and (5) register write – 80 ns. The times required in each stage are shown above
3. Consider a pipeline in a processor that has 5 stages: (1) instruction fetch – 120 ns, (2) instruction decode - 30 ns (3) memory read - 80 ns (4) instruction execution - 30 ns and (5) register write – 80 ns. The times required in each stage are shown above
Computer Networking: A Top-Down Approach (7th Edition)
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3. i and ii no handwriting, please
![3. Consider a pipeline in a processor that has 5 stages: (1) instruction fetch – 120 ns, (2)
instruction decode – 30 ns (3) memory read – 80 ns (4) instruction execution – 30 ns
and (5) register write – 80 ns. The times required in each stage are shown above
following the name of the stage. For example, the instruction fetch requires 120 ns to
complete. Assume that every instruction in the instruction set requires the use of all
stages of the pipeline. Also assume that the stages of the pipeline are clocked with a
common clock. This means that all information moves synchronously through the
pipeline from one stage to the next based on a single clock signal dictating when
information advances from one stage to the next.
(0)
Identify the execution time of a 5000-instruction program without
pipelining.
What can you infer on the latency of an instruction flowing through the
pipeline? (Remember that you have a common clock)
Since all stages of the pipeline are clocked with a single clock, interpret
the fastest frequency of the clock for this pipeline.
Draw your conclusion on the idealised throughput of the pipeline.
(Assume that there are no hazards between instructions).
Assume that the following sequence of instructions is executed by the
(i)
(ii)
(iv)
(v)
processor:
11, 12, 13, 14, 15 with a data hazard between 12 and 13 and a memory
resource hazard between 13 and 15.
Using the Table below, write the instruction that resides in the Memory Read,
Instruction Execution and Register Write stages of the pipeline for each
period (from T1 to T13) taking into consideration the delay required to correct
the data hazard between 12 and 13 and the memory resource hazard
between 13 and 15.
Clock
period
T1
Instruction
Instruction
Memory
Read
Instruction
Write
fetch
decode
execution
back
11
T2
12
T3
T4
T5
T6
T7
T8
T9](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2Faac83b7f-0740-40b6-9c1d-5031eb367da9%2Fd190e5ea-cf33-427d-ad87-cf58f0280892%2F5nhob1k_processed.png&w=3840&q=75)
Transcribed Image Text:3. Consider a pipeline in a processor that has 5 stages: (1) instruction fetch – 120 ns, (2)
instruction decode – 30 ns (3) memory read – 80 ns (4) instruction execution – 30 ns
and (5) register write – 80 ns. The times required in each stage are shown above
following the name of the stage. For example, the instruction fetch requires 120 ns to
complete. Assume that every instruction in the instruction set requires the use of all
stages of the pipeline. Also assume that the stages of the pipeline are clocked with a
common clock. This means that all information moves synchronously through the
pipeline from one stage to the next based on a single clock signal dictating when
information advances from one stage to the next.
(0)
Identify the execution time of a 5000-instruction program without
pipelining.
What can you infer on the latency of an instruction flowing through the
pipeline? (Remember that you have a common clock)
Since all stages of the pipeline are clocked with a single clock, interpret
the fastest frequency of the clock for this pipeline.
Draw your conclusion on the idealised throughput of the pipeline.
(Assume that there are no hazards between instructions).
Assume that the following sequence of instructions is executed by the
(i)
(ii)
(iv)
(v)
processor:
11, 12, 13, 14, 15 with a data hazard between 12 and 13 and a memory
resource hazard between 13 and 15.
Using the Table below, write the instruction that resides in the Memory Read,
Instruction Execution and Register Write stages of the pipeline for each
period (from T1 to T13) taking into consideration the delay required to correct
the data hazard between 12 and 13 and the memory resource hazard
between 13 and 15.
Clock
period
T1
Instruction
Instruction
Memory
Read
Instruction
Write
fetch
decode
execution
back
11
T2
12
T3
T4
T5
T6
T7
T8
T9
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