A computer consists of a processor and an I/O device D connected to main memory M via a shared bus with a data bus width of one word. The processor can execute a maximum of 106 instructions per second. An average instruction requires five ma- chine cycles, three of which use the memory bus. A memory read or write operation uses one machine cycle. Suppose that the processor is continuously executing "background" programs that require 95% of its instruction execution rate but not any I/O instructions. Assume that one processor cycle equals one bus cycle. Now suppose the I/O device is to be used to transfer very large blocks of data between M and D. a. If programmed I/O is used and each one-word I/O transfer requires the processor to execute two instructions, estimate the maximum I/O data-transfer rate, in words per second, possible through D. b. Estimate the same rate if DMA is used.

A computer consists of a processor and an I/O device D connected to main memory M via a shared bus with a data bus width of one word. The processor can execute a maximum of 106 instructions per second. An average instruction requires five ma- chine cycles, three of which use the memory bus. A memory read or write operation uses one machine cycle. Suppose that the processor is continuously executing "background" programs that require 95% of its instruction execution rate but not any I/O instructions. Assume that one processor cycle equals one bus cycle. Now suppose the I/O device is to be used to transfer very large blocks of data between M and D. a. If programmed I/O is used and each one-word I/O transfer requires the processor to execute two instructions, estimate the maximum I/O data-transfer rate, in words per second, possible through D. b. Estimate the same rate if DMA is used.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Consider a hypothetical microprocessor generating a 16-bit address (for example, as- sume that the program counter and the address registers are 16 bits wide) and having a 16-bit data bus. a. What is the maximum memory address space that the processor can access directly if it is connected to a "16-bit memory"? b. What is the maximum memory address space that the processor can access directly if it is connected to an "8-bit memory"? c. What architectural features will allow this microprocessor to access a separate "I/O space"?
Consider a hypothetical microprocessor generating a 16-bit address (for example, as- sume that the program counter and the address registers are 16 bits wide) and having a 16-bit data bus. a. What is the maximum memory address space that the processor can access directly if it is connected to a "16-bit memory"? b. What is the maximum memory address space that the processor can access directly if it is connected to an "8-bit memory"? c. What architectural features will allow this microprocessor to access a separate "I/O space"?
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Consider a hypothetical microprocessor generating a 16-bit address (for example, as- sume that the program counter and the address registers are 16 bits wide) and having a 16-bit data bus. a. What is the maximum memory address space that the processor can access directly if it is connected to a "16-bit memory"? b. What is the maximum memory address space that the processor can access directly if it is connected to an "8-bit memory"? c. What architectural features will allow this microprocessor to access a separate "I/O space"?