Q9) Assume miss rate of an instruction cache is 2% and miss rate of data cache is 4%. If a processor has CPI of 2 without any memory stalls and miss penalty is 100 cycles for all misses, determine how much faster a processor would run with a perfect cache that never missed. Assume frequency of all loads and stores is 36%.
Q9) Assume miss rate of an instruction cache is 2% and miss rate of data cache is 4%. If a processor has CPI of 2 without any memory stalls and miss penalty is 100 cycles for all misses, determine how much faster a processor would run with a perfect cache that never missed. Assume frequency of all loads and stores is 36%.
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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![Q9) Assume miss rate of an instruction cache is 2% and miss rate of data cache is 4%. If a
processor has CPI of 2 without any memory stalls and miss penalty is 100 cycles for all
misses, determine how much faster a processor would run with a perfect cache that never
missed. Assume frequency of all loads and stores is 36%.
Q10) For a cache memory of size 32 KB, how many cache lines (blocks) does the cache hold
for block sizes of 32 or 64 bytes?](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F58a8b645-fc84-4386-8356-edd0150531a2%2F84f8db0e-6fd5-438e-9fb6-37f5cbadb947%2Fii7s3i_processed.png&w=3840&q=75)
Transcribed Image Text:Q9) Assume miss rate of an instruction cache is 2% and miss rate of data cache is 4%. If a
processor has CPI of 2 without any memory stalls and miss penalty is 100 cycles for all
misses, determine how much faster a processor would run with a perfect cache that never
missed. Assume frequency of all loads and stores is 36%.
Q10) For a cache memory of size 32 KB, how many cache lines (blocks) does the cache hold
for block sizes of 32 or 64 bytes?
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