1. When a program is adapted to run on multiple cores in a multiprocessor system, the executiontime on each core is comprised of computing time and the overhead time required for lockedcritical sections and/or to send data from one core to another.Assume a program requires t = 200 sec of execution time on one core. When run on n cores,each core requires t/n sec, as well as an additional 10 sec of overhead, irrespective of thenumber of cores.a. Compute the per-core execution time for 2, 4, 8, 16, 32, 64, and 128 cores.b. For each case, list the corresponding speedup relative to a single core and the ratiobetween actual speedup versus ideal speedup (speedup if there was no overhead).

Here is the explanation of the above problem. see below steps.

Answered: 1. When a program is adapted to run on…

Computer Networking: A Top-Down Approach (7th Edition)

7th Edition

ISBN:9780133594140

Author:James Kurose, Keith Ross

Publisher:James Kurose, Keith Ross

Chapter1: Computer Networks And The Internet

Section: Chapter Questions

Problem R1RQ: What is the difference between a host and an end system? List several different types of end...

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8 A computer consists of a processor and an I/O device D connected to main memory M via a shared bus with a data bus width of one word. The processor can execute a maximum of 106 instructions per second. An average instruction requires five ma- chine cycles, three of which use the memory bus. A memory read or write operation uses one machine cycle. Suppose that the processor is continuously executing "background" programs that require 95% of its instruction execution rate but not any I/O instructions. Assume that one processor cycle equals one bus cycle. Now suppose the I/O device is to be used to transfer very large blocks of data between M and D. a. If programmed I/O is used and each one-word I/O transfer requires the processor to execute two instructions, estimate the maximum I/O data-transfer rate, in words per second, possible through D. b. Estimate the same rate if DMA is used.
You are given an instruction set architecture (ISA) with a variable-length instruction encoding scheme and instruction categories for a test program as tabulated in Table 1. Table 1: Instruction Categories and Encoding Scheme Instruction Length (bits) Instruction Category Frequency 40% 24 ALU operations Loads Stores 32 32 20% 20% 20% 16 Branches A. Compute the average instruction length (AIL) for the variable-length instruction encoding scheme in Table 1. B. Compute the memory storage requirements (in bytes) for the test program under the variable-length instruction encoding scheme (Table 1) if it contains 1 billion (i.e., 1 x 10º) instructions. C. Compute the memory savings (as a percentage) compared to a baseline fixed-length instruction encoding scheme with 32 bits per instruction for the test program with 1 billion (i.e., 1 x 10°) instructions.
A large endian byte addressed memory system with eight distinct memory modules is included in a computer system. Each memory module has 134217728 cells and is 32 bits wide. a) What is the 32-bit memory address of cell 1048578 in module 3 if the memory uses high order interleaving? b) What is the 32-bit memory address of byte 1048575 inside module 2 if the memory uses high order interleaving? c) What is the 32-bit memory address of cell 511 inside module 1 if the high order interleaved memory utilises little endian storage order instead of big endian storage order?
Assume miss rate of an instruction cache is 2% and miss rate of data cache IS 4%, If a processor have CPI of 2 without any memory stalls and miss penalty is 100 cycles for all misses, determine how much faster a processor would run with a perfect cache that never missed. Assume frequency of all loads and stores is 36%.
Consider a DRAM chip of capacity 256 KB and each memory location contains 8 bits. The memory chip is organized in matrix form with equal number of rows and column for each memory location of 8 bits. This DRAM chip has a refresh interval of 64 ms, memory bus runs at 200 MHz, and the refresh cycle takes 4 clock cycle. a) Time required to refresh the DRAM chip. b) What is the minimum size of the refresh counter?
Calculate the CPU execution time (expressed in milliseconds) of a program with 10 million instructions on a 2.5 GHz CPU with the following basic instruction-type breakdowns and CPIs: Arithmetic: 60%, CPI = 2 Load & Store (assuming perfect caches): 25%, CPI = 5 Branching: 15%, CPI = 3 In addition, you are told that the overall cache miss rate for instructions is 1%, the overall cache miss rate for data is 3%, and the cache miss penalty is 100 cycles. You can ignore the hit time (consider it zero).
A certain microprocessor requires either 2, 4, 8, 12, or 16 machine cycles to perform various operations. A total of 17.5% of its instructions require 2 machine cycles, 12.5% require 4 machine cycles, 35% require 8 machine cycles, 20% require 12 machine cycles, and 15% require 16 machine cycles.Q) What is the clock rate (machine cycles per second) required for this microprocessor to be a “1 MIPS” processor?
Consider the execution of a program that results in the execution of 8 million instructions on a 400-MHz processor. The program consists of four major types of instructions. The instruction mix and the CPI for each instruction type are given below. What is the program execution time in the second? Instruction Type Arithmetic and logic Load/store with cache hit Branch Floating-point arithmetic operation Execution Time: sec CPI 3 4 3 9 Instruction Mix (%) 60 20 12 8
A multiprocessor consists of 100 processors, each capable of a peak execution rate of 2Gflops. What is the performance of the system as measured in Gflops when 2% of the code is sequential and 98% is parallelizable?

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