f. Compare the actual speedup factor provided by Machine C over Machine B with the theoretical speedup factor determined by Amdahl's law assuming that none of the code is inherently serial. All of it is parallelizable, with no scheduling overhead.

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
Topic Video
Question
Solve part F
f. Compare the actual speedup factor provided by Machine C over Machine B with the
theoretical speedup factor determined by Amdahl's law assuming that none of the code is
inherently serial. All of it is parallelizable, with no scheduling overhead.
Transcribed Image Text:f. Compare the actual speedup factor provided by Machine C over Machine B with the theoretical speedup factor determined by Amdahl's law assuming that none of the code is inherently serial. All of it is parallelizable, with no scheduling overhead.
c. Now assume that the program can be executed in 4 parallel tasks or threads with roughly
equal number of instructions executed in each task. In another words, as the program is
parallelized to run over multiple cores, the number of instructions per processor is divided
by the number of cores. Execution is on a quadcore system with each core (processor)
having the same performance as the single processor originally used for Machine B.
Coordination and synchronization between the parts adds an extra 50,000 instruction
executions to each task. Assume the same instruction mix as for Machine B for each task,
but increase the CPI for memory reference with cache miss to 10 cycles due to contention
for memory.
Fill out the table below for Machine C.
Machine
B
Instruction Type
Logic and Arithmetic
Branch
Load Store with cache hit
Memory reference with cache miSS
Logic and Arithmetic
Load/Store with cache hit
Memory reference with cache miss
1
1
8
Instruction Mix (9)
10
60
Transcribed Image Text:c. Now assume that the program can be executed in 4 parallel tasks or threads with roughly equal number of instructions executed in each task. In another words, as the program is parallelized to run over multiple cores, the number of instructions per processor is divided by the number of cores. Execution is on a quadcore system with each core (processor) having the same performance as the single processor originally used for Machine B. Coordination and synchronization between the parts adds an extra 50,000 instruction executions to each task. Assume the same instruction mix as for Machine B for each task, but increase the CPI for memory reference with cache miss to 10 cycles due to contention for memory. Fill out the table below for Machine C. Machine B Instruction Type Logic and Arithmetic Branch Load Store with cache hit Memory reference with cache miSS Logic and Arithmetic Load/Store with cache hit Memory reference with cache miss 1 1 8 Instruction Mix (9) 10 60
Expert Solution
Step 1: Here is the conceptual introduction:

To calculate the speedup factor provided by Machine C over Machine B, it needs to consider the parallel execution of tasks on a quad-core system with synchronization overhead and increased CPI for memory references with cache misses. It will calculate the execution time for both Machine B and Machine C and then find the speedup factor.

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