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c. Now assume that the program can be executed in 4 parallel tasks or threads with roug equal number of instructions executed in each task. In another words, as the program parallelized to run over multiple cores, the number of instructions per processor is divid by the number of cores. Execution is on a quadcore system with each core (processc having the same performance as the single processor originally used for Machine Coordination and synchronization between the parts adds an extra 50,000 instructic executions to each task. Assume the same instruction mix as for Machine B for each tas but increase the CPI for memory reference with cache miss to 10 cycles due to contentio. for memory.

c. Now assume that the program can be executed in 4 parallel tasks or threads with roug equal number of instructions executed in each task. In another words, as the program parallelized to run over multiple cores, the number of instructions per processor is divid by the number of cores. Execution is on a quadcore system with each core (processc having the same performance as the single processor originally used for Machine Coordination and synchronization between the parts adds an extra 50,000 instructic executions to each task. Assume the same instruction mix as for Machine B for each tas but increase the CPI for memory reference with cache miss to 10 cycles due to contentio. for memory.

Database System Concepts
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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Please use the info to solve part c

Consider two different machines A and B, with two different instruction sets. Machine A has a clock rate of 200 MHz while Machine B has a clock rate of 4 GHz. Assume a given program of 4 million instructions is being executed on both machines A and B. The program consists of four major types of instructions. The instruction mix and the CPI for each instruction type are given below: Machine A B Instruction Type Logic and Arithmetic Branch Load/Store with cache hit Memory reference with cache miss Logic and Arithmetic Branch Load/Store with cache hit Memory reference with cache miss CPI 2 4 8 16 1 2 4 8 Instruction Mix (%) 60 18 12 10 10 12 18 60
Transcribed Image Text:Consider two different machines A and B, with two different instruction sets. Machine A has a clock rate of 200 MHz while Machine B has a clock rate of 4 GHz. Assume a given program of 4 million instructions is being executed on both machines A and B. The program consists of four major types of instructions. The instruction mix and the CPI for each instruction type are given below: Machine A B Instruction Type Logic and Arithmetic Branch Load/Store with cache hit Memory reference with cache miss Logic and Arithmetic Branch Load/Store with cache hit Memory reference with cache miss CPI 2 4 8 16 1 2 4 8 Instruction Mix (%) 60 18 12 10 10 12 18 60
c. Now assume that the program can be executed in 4 parallel tasks or threads with roughly equal number of instructions executed in each task. In another words, as the program is parallelized to run over multiple cores, the number of instructions per processor is divided by the number of cores. Execution is on a quadcore system with each core (processor) having the same performance as the single processor originally used for Machine B. Coordination and synchronization between the parts adds an extra 50,000 instruction executions to each task. Assume the same instruction mix as for Machine B for each task, but increase the CPI for memory reference with cache miss to 10 cycles due to contention for memory. Fill out the table below for Machine C. Machine B C Instruction Type Logic and Arithmetic Branch Load/Store with cache hit Memory reference with cache miss Logic and Arithmetic Branch Load/Store with cache hit Memory reference with cache miss CPI 1 4 8 Instruction Mix (%) 10 12 18 60
Transcribed Image Text:c. Now assume that the program can be executed in 4 parallel tasks or threads with roughly equal number of instructions executed in each task. In another words, as the program is parallelized to run over multiple cores, the number of instructions per processor is divided by the number of cores. Execution is on a quadcore system with each core (processor) having the same performance as the single processor originally used for Machine B. Coordination and synchronization between the parts adds an extra 50,000 instruction executions to each task. Assume the same instruction mix as for Machine B for each task, but increase the CPI for memory reference with cache miss to 10 cycles due to contention for memory. Fill out the table below for Machine C. Machine B C Instruction Type Logic and Arithmetic Branch Load/Store with cache hit Memory reference with cache miss Logic and Arithmetic Branch Load/Store with cache hit Memory reference with cache miss CPI 1 4 8 Instruction Mix (%) 10 12 18 60
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