Recall that we have two write policies and write allocation policies, and their combinations can be implemented either in L1 or L2 cache. Assume the following choices for L1 and L2 caches: L1 L2 Write through, non-write allocate Write back, write allocate 1. Buff ers are employed between diff erent levels of memory hierarchy to reduce access latency. For this given confi guration, list the possible buff ers needed between L1 and L2 caches, as well as L2 cache and memory.2. Describe the procedure of handling an L1 write-miss, considering the component involved and the possibility of replacing a dirty block.3. For a multilevel exclusive cache (a block can only reside in one of the L1 and L2 caches), confi guration, describe the procedure of handling an L1 write-miss, considering the component involved and the possibility of replacing a dirty block.Consider the following program and cache behaviors. Data Reads per1000 Instructions Data Writes per1000 Instructions Instruction CacheMiss Rate Data CacheMiss Rate Block Size(byte) 250 100 0.30% 2% 64 For a write-through, write-allocate cache, what are the minimum read and write bandwidths (measured by byte per cycle) needed to achieve a CPI of 2?For a write-back, write-allocate cache, assuming 30% of replaced data cache blocks are dirty, what are the minimal read and write bandwidths needed for a CPI of 2?What are the minimal bandwidths needed to achieve the performance of CPI=1.5?
Recall that we have two write policies and write allocation policies, and their combinations can be implemented either in L1 or L2 cache. Assume the following choices for L1 and L2 caches:
| L1 | L2 |
| Write through, non-write allocate | Write back, write allocate |
1. Buff ers are employed between diff erent levels of memory hierarchy to reduce access latency. For this given confi guration, list the possible buff ers needed between L1 and L2 caches, as well as L2 cache and memory.
2. Describe the procedure of handling an L1 write-miss, considering the component involved and the possibility of replacing a dirty block.
3. For a multilevel exclusive cache (a block can only reside in one of the L1 and L2 caches), confi guration, describe the procedure of handling an L1 write-miss, considering the component involved and the possibility of replacing a dirty block.
Consider the following program and cache behaviors.
| Data Reads per 1000 Instructions |
Data Writes per 1000 Instructions |
Instruction Cache Miss Rate |
Data Cache Miss Rate |
Block Size (byte) |
| 250 | 100 | 0.30% | 2% | 64 |
For a write-through, write-allocate cache, what are the minimum read and write bandwidths (measured by byte per cycle) needed to achieve a CPI of 2?
For a write-back, write-allocate cache, assuming 30% of replaced data cache blocks are dirty, what are the minimal read and write bandwidths needed for a CPI of 2?
What are the minimal bandwidths needed to achieve the performance of CPI=1.5?
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