Cache access involves virtual to physical address translation through the TLB, cache tag comparison through the tag array, and cache data access through the data array as shown in the diagram below. a.  Is TLB a direct-mapped, or a n-way set-associative, or a fully associative design? If it is a set-associate, what is the value of n? b. Is cache direct-mapped, or a n-way set-associative, or a fully associative design? If it is a set-associate, what is the value of n? c. What is the cache block size? d.  What is the

Computer Networking: A Top-Down Approach (7th Edition)
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ISBN:9780133594140
Author:James Kurose, Keith Ross
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Cache access involves virtual to physical address translation through the TLB, cache tag comparison through the tag array, and cache data access through the data array as shown
in the diagram below.
a.  Is TLB a direct-mapped, or a n-way set-associative, or a fully associative
design? If it is a set-associate, what is the value of n?
b. Is cache direct-mapped, or a n-way set-associative, or a fully associative
design? If it is a set-associate, what is the value of n?
c. What is the cache block size?
d.  What is the cache size (only consider the data array)?

Virtual address
31 30 29
..... 14 13 12 11 10 9........ 3 2 1 0
Page offset
12
Virtual page number
J20
Valid Dirty
Tag
Physical page number
TLB
TLB hit +.
20
Physical page number
Page offset
-Physical address-
Cache index
Block
Physical address tag
Byte
offset
offset
4
18
8
12
Data
Valid
Tag
Cache
Cache hit -
32
Data
O00000
Transcribed Image Text:Virtual address 31 30 29 ..... 14 13 12 11 10 9........ 3 2 1 0 Page offset 12 Virtual page number J20 Valid Dirty Tag Physical page number TLB TLB hit +. 20 Physical page number Page offset -Physical address- Cache index Block Physical address tag Byte offset offset 4 18 8 12 Data Valid Tag Cache Cache hit - 32 Data O00000
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