For each of the cache modifications that we could perform, select whether it will increase, decrease, have no effect, or have an unknown effect on the parameter. • An unknown effect means that it could either decrease or increase the parameter in question. • No effect also includes marginal or very little effect • When answering for multilevel caching, answer based on the caching system as a whole. Improvement Increase Cache Size (C) Increase Associativity(K) Increase Block Size(b) Use Multilevel Caching Hit Rate [Select] [Select] [Select] [Select] < Cache Access Time [Select] [Select] [Select] [Select] Average Memory Access Time V [Select] V [Select] [Select] [Select] <

For each of the cache modifications that we could perform, select whether it will increase, decrease, have no effect, or have an unknown effect on the parameter. • An unknown effect means that it could either decrease or increase the parameter in question. • No effect also includes marginal or very little effect • When answering for multilevel caching, answer based on the caching system as a whole. Improvement Increase Cache Size (C) Increase Associativity(K) Increase Block Size(b) Use Multilevel Caching Hit Rate [Select] [Select] [Select] [Select] < Cache Access Time [Select] [Select] [Select] [Select] Average Memory Access Time V [Select] V [Select] [Select] [Select] <

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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8 Task 6: Launching Attack on 64-bit Program (Level 4) The target program (stack-L4) in this task is similar to the one in the Level 2, except that the buffer size is extremely small. We set the buffer size to 10, while in Level 2, the buffer size is much larger. Your goal is the same: get the root shell by attacking this Set-UID program. You may encounter additional challenges in this attack due to the small buffer size. If that is the case, you need to explain how your have solved those challenges in your attack.
Suppose a byte-addressable computer using set associative cache has 224 bytes of main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
Think about the difference that exists between a cache that is totally associative and one that is directly mapped. This is a distinction that has to be made.
Is there a way to find out which parts of a log entry a certain log processing function can read? The following code determines the typical number of cache misses per entry while using 64-byte cache blocks and no prefetching.
The write buffer sends a block back to main memory while the processor issues a request that the cache cannot fulfill. What ought to occur in this scenario?
Make the difference between a cache that is directly mapped and one that is totally associative.
Match each type of miss with its definition. Compulsory Miss Capacity Miss Conflict Miss ✓ [Choose ] A miss that occurs because this is the first time we have accessed the block that contains the desired value A miss that occurs because the values that we are working on both map to the same place in the cache and therefore can't both A miss that occurs because we are unable to fit all of the values that we are working on inside the cache [Choose ]
1. Concerning the memory hierarchy, there is a trade-off among the three key characteristics: capacity, access time, and cost. What is the relationship between these three? 2. What happens if a computer system only contains registers and main memory, but no cache? Justify your answer 3. The replacement algorithm chooses (within the constraints of the mapping function) which block to replace when a new block is to be loaded into the cache and the cache already has all slots filled with other blocks. Suggest a strategy that has at least one advantage over the least-recently-used (LRU) algorithm. Justify your answer
Suppose a byte-addressable computer using set associative cache has 8M byes of main memory and a cache of 128 blocks, where each cache block contains 64 bytes. a) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 16-way set associative, what is the format of a memory address as seen by the cache
For the cache design of the preceding problem, suppose that increasing the line size from one word to four words results in a decrease of the read miss rate from 3.2% to 1.1%. For both the nonburst transfer and the burst transfer case, what is the average miss penalty, averaged over all reads, for the two different line sizes?
please i just need Clear answer with screen shot for output if needed
Please provide explanation.