Concerning the memory hierarchy, there is a trade-off among the three key characteristics: capacity, access time, and cost. What is the relationship between these three? What happens if a computer system only contains registers and main memory, but no cache? Justify your answer The replacement algorithm chooses (within the constraints of the mapping function) which block to replace when a new block is to be loaded into the cache and the cache already has all slots filled with other blocks. Suggest a strategy that has at least one advantage over the least-recently-used (LRU) algorithm. Justify your answer

Concerning the memory hierarchy, there is a trade-off among the three key characteristics: capacity, access time, and cost. What is the relationship between these three? What happens if a computer system only contains registers and main memory, but no cache? Justify your answer The replacement algorithm chooses (within the constraints of the mapping function) which block to replace when a new block is to be loaded into the cache and the cache already has all slots filled with other blocks. Suggest a strategy that has at least one advantage over the least-recently-used (LRU) algorithm. Justify your answer

Computer Networking: A Top-Down Approach (7th Edition)

7th Edition

ISBN:9780133594140

Author:James Kurose, Keith Ross

Publisher:James Kurose, Keith Ross

Chapter1: Computer Networks And The Internet

Section: Chapter Questions

Problem R1RQ: What is the difference between a host and an end system? List several different types of end...

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iz Instructions through the questions for each of the sections. You may submit this exercise twice. Consider a memory of size 8KB (8192 bytes) that allows dynamic, variable sized partitioning among processes and uses a linked list to keep track of free spaces (hereafter referred to as the free list) in the memory at any given time. Assume that there are 6 processes and assume that their memory size requirements (in bytes) are as given below: P1: 500, P2: 600, P3: 1300, P4: 2000, P5: 100, P6: 200 Assume that the initial state of the free list is as shown below (BA is the base address and Sz is the size of each free space): BA: 0; Sz: 1100 BA: 1200: Sz: 600 BA: 2000; Sz: 1800→BA: 6000; Sz 400 in its initial state Assume that the next fit policy
Suppose we have a system with the following properties:The memory is byte addressable.Memory accesses are to 1-byte words (not to 4-byte words).Addresses are 13 bits wide.The cache is 4-way set associative (E = 4), with a 4-byte block size(B = 4) and eight sets (S = 8).Consider the following cache state. All addresses, tags, and valuesare given in hexadecimal format. The Index column contains the set index for each set of four lines. The Tag columns contain the tag value for each line. The V columns contain the valid bit for each line. The Bytes 0−3 columns contain the data for each line, numbered left to right starting with byte 0 on the left. A. What is the size (C) of this cache in bytes?B. The box that follows shows the format of an address (1 bit perbox). Indicate (by labeling the diagram) the fields that would beused to determine the following:CO. The cache block offsetCI. The cache set indexCT. The cache tag
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For the cache design of the preceding problem, suppose that increasing the line size from one word to four words results in a decrease of the read miss rate from 3.2% to 1.1%. For both the nonburst transfer and the burst transfer case, what is the average miss penalty, averaged over all reads, for the two different line sizes?
There are many parameters that could be used to describe disk performance; among them are: number of bits per track disk capacity (in bits) number of disk surfaces rotational speed rotational latency transfer rate tracks per surface sectors per track blocks per track sectors per block seek time speed of disk arm block-read time number of blocks Some of these parameters are independent, and others are (approximately) linearly related. That is, doubling one doubles the other. Decide which of these parameters are linearly related. Then, select from the list below, the relationship that is true, to within a close approximation. Note: none of the statements may be true exactly, but one will always be much closer to the truth than the other three. Also note: you should assume all dimensions and parameters of the disk are unchanged except for the ones mentioned. a) If you divide tracks into half as many blocks, then you double the read time for a block.…
Take into account the following scenario: we have a byte-addressable computer with 2-way set associative mapping, 16-bit main memory addresses, and 32 blocks of cache memory. Since there are 8 bytes in a block, you can use that information to calculate how big the offset field has to be.
Consider a memory of size 8KB (8192 bytes) that allows dynamic, variable sized partitioning among processes and uses a linked list to keep track of free spaces (hereafter referred to as the free list) in the memory at any given time. Assume that there are 6 processes and assume that their memory size requirements (in bytes) are as given below: Р1: 500, Р2: 600, Р3: 1300, Р4: 2000, Р5: 100, Р6: 200 Assume that the initial state of the free list is as shown below (BA is the base address and Sz is the size of each free space): ВА: 0; Sz: 1100 — ВА: 1200; Sz: 600 > BА: 2000; Sz: 1800> ВА: 6000%; Sz 400
1. Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses. 42, 137, 66, 50, 38, 225, 173, 22, 19, 88, 51, 43 a. For each of these references, identify the binary address, the tag, and the index given a direct mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. b. For each of these references, identify the binary address, the tag, and the index given a direct mapped cache with two-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. Please explain the process.
Suppose we have a byte-addressable computer with a cache that holds 16 blocks of 4 bytes address has 8 bits, to which cache set would the hexadecimal address OxBE map if the computer mapping? each. Assuming that each memory uses 2-way set associative
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Let's pretend for a moment that we have a byte-addressable computer with fully associative mapping, 16-bit main memory addresses, and 32 blocks of cache memory. The following holds true if each block is 16 bits in size: a) Determine how many bytes the offset field is. Measure the tag field's width and height in pixels (b).
Take into account the following scenario: we have a byte-addressable computer with 2-way set associative mapping, 16-bit main memory addresses, and 32 blocks of cache memory. Since there are 8 bytes in a block, you can use that information to calculate how big the offset field has to be.