The contents of the cache are as follows, with all addresses, tags, and values given in hexadecimal notation: B. For each of the following memory accesses, indicate if it will be a cache hit or miss when carried out in sequence as listed. Also Set index Tag Valid Byte 0 Byte 1 Byte 2 Byte 3 give the value of a read if it can be inferred from the information in the cache, 00 1 40 41 42 43 Operation Address Hit? Read value (or unknown) 83 1 FE 97 CC DO 1 00 44 45 46 47 Read Ох834 83 Write Ox836 2 00 1 48 49 4A 4B Read OXFFD 40 3 FF 1 9A CO 03 FF 00 A. The following diagram shows the format of an address (1 bit per box). Indicate (by labeling the diagram) the fields that would be used to determine the following: CO. The cache block offset CI. The cache set index CT. The cache tag 12 11 10 A A 7 A5 4 A ? 1 n
The contents of the cache are as follows, with all addresses, tags, and values given in hexadecimal notation: B. For each of the following memory accesses, indicate if it will be a cache hit or miss when carried out in sequence as listed. Also Set index Tag Valid Byte 0 Byte 1 Byte 2 Byte 3 give the value of a read if it can be inferred from the information in the cache, 00 1 40 41 42 43 Operation Address Hit? Read value (or unknown) 83 1 FE 97 CC DO 1 00 44 45 46 47 Read Ох834 83 Write Ox836 2 00 1 48 49 4A 4B Read OXFFD 40 3 FF 1 9A CO 03 FF 00 A. The following diagram shows the format of an address (1 bit per box). Indicate (by labeling the diagram) the fields that would be used to determine the following: CO. The cache block offset CI. The cache set index CT. The cache tag 12 11 10 A A 7 A5 4 A ? 1 n
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Question
Suppose we have a system with the following properties:
The memory is byte addressable.
Memory accesses are to 1-byte words (not to 4-byte words).
Addresses are 12 bits wide.
The cache is two-way set associative (E = 2), with a 4-byte block
size (B = 4) and four sets (S = 4).
Transcribed Image Text:The contents of the cache are as follows, with all addresses, tags, and
values given in hexadecimal notation:
B. For each of the following memory accesses, indicate if it will be
a cache hit or miss when carried out in sequence as listed. Also
Set index
Tag
Valid
Byte 0
Byte 1
Byte 2
Byte 3
give the value of a read if it can be inferred from the information
in the cache,
00
1
40
41
42
43
Operation
Address
Hit?
Read value (or unknown)
83
1
FE
97
CC
DO
1
00
44
45
46
47
Read
Ох834
83
Write
Ox836
2
00
1
48
49
4A
4B
Read
OXFFD
40
3
FF
1
9A
CO
03
FF
00
A. The following diagram shows the format of an address (1 bit
per box). Indicate (by labeling the diagram) the fields that would
be used to determine the following:
CO. The cache block offset
CI. The cache set index
CT. The cache tag
12 11 10 A A 7
A5 4 A ? 1 n
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