Match each type of miss with its definition. Compulsory Miss Capacity Miss Conflict Miss ✓ [Choose ] A miss that occurs because this is the first time we have accessed the block that contains the desired value A miss that occurs because the values that we are working on both map to the same place in the cache and therefore can't both A miss that occurs because we are unable to fit all of the values that we are working on inside the cache [Choose ]

Match each type of miss with its definition. Compulsory Miss Capacity Miss Conflict Miss ✓ [Choose ] A miss that occurs because this is the first time we have accessed the block that contains the desired value A miss that occurs because the values that we are working on both map to the same place in the cache and therefore can't both A miss that occurs because we are unable to fit all of the values that we are working on inside the cache [Choose ]

Computer Networking: A Top-Down Approach (7th Edition)

7th Edition

ISBN:9780133594140

Author:James Kurose, Keith Ross

Publisher:James Kurose, Keith Ross

Chapter1: Computer Networks And The Internet

Section: Chapter Questions

Problem R1RQ: What is the difference between a host and an end system? List several different types of end...

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Question

### Cache Miss Types Matching Activity

**Instructions:**

Match each type of cache miss with its correct definition from the options provided in the drop-down menus.

1. **Compulsory Miss**
- [Choose]
- A miss that occurs because this is the first time we have accessed the block that contains the desired value
- A miss that occurs because the values that we are working on both map to the same place in the cache and therefore can't both
- A miss that occurs because we are unable to fit all of the values that we are working on inside the cache

2. **Capacity Miss**
- [Choose]
- A miss that occurs because this is the first time we have accessed the block that contains the desired value
- A miss that occurs because the values that we are working on both map to the same place in the cache and therefore can't both
- A miss that occurs because we are unable to fit all of the values that we are working on inside the cache

3. **Conflict Miss**
- [Choose]
- A miss that occurs because this is the first time we have accessed the block that contains the desired value
- A miss that occurs because the values that we are working on both map to the same place in the cache and therefore can't both
- A miss that occurs because we are unable to fit all of the values that we are working on inside the cache

Ensure you select the correct definitions to better understand the three different cache miss types.

For each action, match it with when it occurs. For this problem, assume the cache is a K-way set associative cache using a Least Recently Used replacement policy.

1. **Valid Bit is set to 0 when**
- Options:
- The computer is turned on
- The CPU writes to this block in the cache
- The cache is full
- The cache reads a block from memory
- The block is not in the set the block maps to and the set is full
- A block that maps to that set is read or written to

2. **Valid bit is set to 1 when**
- [Choose from options listed above]

3. **Dirty Bit is set to 0 when**
- [Choose from options listed above]

4. **Dirty Bit is set to 1 when**
- [Choose from options listed above]

5. **A block is evicted from the cache when**
- [Choose from options listed above]

6. **Tag bits are written to when**
- [Choose from options listed above]

7. **The LRU counters of a set are updated when**
- [Choose from options listed above]

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