3. Consider the code segment we discussed in class.Assume N = 32 and using a direct mappedcache with parameters (m; S; E; B) = (32; 8; 1; 8).Describe cache hits and misses during theexecution of the code.int data [N];int abc ()int suml = 0, sum2 = 0, result;int i;for (i=0; i < N; i++)suml += data[i];}suml /= N;for (i=0; i < N; i++){sum2+= data[i] * data[i];sum2 /= N;result =(sum2- suml*suml);return result;}

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Answered: 3. Consider the code segment we…

Computer Networking: A Top-Down Approach (7th Edition)

7th Edition

ISBN:9780133594140

Author:James Kurose, Keith Ross

Publisher:James Kurose, Keith Ross

Chapter1: Computer Networks And The Internet

Section: Chapter Questions

Problem R1RQ: What is the difference between a host and an end system? List several different types of end...

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3. Assuming a cache of 4096 blocks, a four-word block size, each word contains 4 bytes, and a 64-bits memory address. Memory is byte addressable, and random block replacement policy and write back policy are implemented. Find the total number of tag bits for caches that are a) direct-mapped b) 2-way set associative c) 4-way set associative d) Fully associative
Given the following setup, how many words can be stored in the cache at the same time when the cache is full? A. Direct mapped cache Tag (T) Index (I) Word (W) Byte (B) 17 11 2 2 B. 2-way associative cache Tag (T) Index (I) Word (W) Byte (B) 18 10 2 2 C. 4-way associative cache Tag (T) Index (I) Word (W) Byte (B) 19 9 2 2 D. Fully associative cache Tag (T) Index (I) Word (W) Byte (B) 28 0 2 2
Please provide explanation.
For each of the cache modifications that we could perform, select whether it will increase, decrease, have no effect, or have an unknown effect on the parameter. • An unknown effect means that it could either decrease or increase the parameter in question. • No effect also includes marginal or very little effect . • When answering for multilevel caching, answer based on the caching system as a whole. Improvement Increase Cache Size (C) Increase Associativity(K) Increase Block Size(b) Use Multilevel Caching Hit Rate [Select] [Select] [Select] [Select] V Cache Access Time [Select] [Select] V [Select] [Select] V Average Memory Access Time [Select] [Select] [Select] [Select] <
Fill in blank Suppose that linear page table is used where the memory addresses are 12-bit binary numbers and the page size is 256 bytes. If a virtual address in binary format is 101000011100, then the VPN (virtual page number) in binary format will be ---------
1. Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses. 42, 137, 66, 50, 38, 225, 173, 22, 19, 88, 51, 43 a. For each of these references, identify the binary address, the tag, and the index given a direct mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. b. For each of these references, identify the binary address, the tag, and the index given a direct mapped cache with two-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. Please explain the process.
Assume a cache of 1 MB organized as 32 bytes each line. The main memory is 256 MB. a. Determine the number of blocks in main memory b. Determine how to split the address (s-r, r, w) for direct mapping. c. Determine how to split the address (s, w) for associative mapping. d. Determine how to split the address (s-d, d, w) for set-associative each cache set is 4 lines of the cache.
Question 24 Some portion of cache system B represented a 2-way set-associative mapping cache system. The system is byte-addressable and the block size is one word (4 bytes). The tag and set number are represented with a binary numbers. The contents of words in the block are represented with hexadecimal. Tag 10 1000 0100 1001 11 1100 0100 1001 10 1000 0100 1001 11 1100 0100 1101 10 1000 0100 1001 11 1100 0100 1001 10 1000 0100 1001 11 1100 0100 1101 10 1000 0100 1001 11 1100 0100 1001 10 1000 0100 1001 11 1100 0100 1101 Set Number 0110 1101 0110 1101 0110 1110 0110 1110 0110 1111 0110 1111 0111 0000 0111 0000 0111 0001 0111 0001 0111 0010 0111 0010 00 2. What is the size of cache memory? Word within block 01 2016 6116 C116 10 3216 7216 C216 4216 8216 4116 5216 9216 8216 3216 4216 8216 6116 1. What is the size of the main memory for cache system B? 11 2116 D216 2016 6116 D116 3216 7216 C216 D216 A216 B216 5116 5216 A216 5216 2716 6116 C116 7216 C216 A216 8216 4116 A216 5216 9216 5216…

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3. Consider the code segment we discussed in class. Assume N = 32 and using a direct mapped cache with parameters (m; S; E; B) = (32; 8; 1; 8). Describe cache hits and misses during the execution of the code.