Question 24 Some portion of cache system B represented a 2-way set-associative mapping cache system. The system is byte-addressable and the block size is one word (4 bytes). The tag and set number are represented with a binary numbers. The contents of words in the block are represented with hexadecimal. Tag 10 1000 0100 1001 11 1100 0100 1001 10 1000 0100 1001 11 1100 0100 1101 10 1000 0100 1001 11 1100 0100 1001 10 1000 0100 1001 11 1100 0100 1101 10 1000 0100 1001 11 1100 0100 1001 10 1000 0100 1001 11 1100 0100 1101 Set Number 0110 1101 0110 1101 0110 1110 0110 1110 0110 1111 0110 1111 0111 0000 0111 0000 0111 0001 0111 0001 0111 0010 0111 0010 00 2. What is the size of cache memory? 2016 6116 C116 4216 3216 7216 5216 Word within block 01 10 3216 A216 C216 8216 9216 8216 3216 7216 C216 2716 6116 1. What is the size of the main memory for cache system B? 4116 11 2016 6116 D116 5116 2116 D216 A216 4216 8216 6116 1216 5216 A216 5216 B216 B216 D216 C116 2116 7216 C216 D216 8216 4116 A216 5216 9216 5216 B216 3. If we request memory read from memory address F1 35 C3, what data do we read? 4. If we request memory read from memory address A1 25 BA, what data do we read?

Question 24 Some portion of cache system B represented a 2-way set-associative mapping cache system. The system is byte-addressable and the block size is one word (4 bytes). The tag and set number are represented with a binary numbers. The contents of words in the block are represented with hexadecimal. Tag 10 1000 0100 1001 11 1100 0100 1001 10 1000 0100 1001 11 1100 0100 1101 10 1000 0100 1001 11 1100 0100 1001 10 1000 0100 1001 11 1100 0100 1101 10 1000 0100 1001 11 1100 0100 1001 10 1000 0100 1001 11 1100 0100 1101 Set Number 0110 1101 0110 1101 0110 1110 0110 1110 0110 1111 0110 1111 0111 0000 0111 0000 0111 0001 0111 0001 0111 0010 0111 0010 00 2. What is the size of cache memory? 2016 6116 C116 4216 3216 7216 5216 Word within block 01 10 3216 A216 C216 8216 9216 8216 3216 7216 C216 2716 6116 1. What is the size of the main memory for cache system B? 4116 11 2016 6116 D116 5116 2116 D216 A216 4216 8216 6116 1216 5216 A216 5216 B216 B216 D216 C116 2116 7216 C216 D216 8216 4116 A216 5216 9216 5216 B216 3. If we request memory read from memory address F1 35 C3, what data do we read? 4. If we request memory read from memory address A1 25 BA, what data do we read?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

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Types of database architectures

A Database Architecture represents the Database Management System’s (DBMS) design (schema). The DBMS architecture makes it easy to understand the components involved in the database system and their relations. The DBMS architecture may vary based on the system on which it runs. Some systems contain both client and server machines whereas some run only on a server machine. Based on the architecture, the system can be classified as centralized, decentralized, or hierarchical.

Question

5. If we access memory in the following order in cache system B:
A1 FF B8
B1 FF B8
A1 FF B8
B1 FF B8
A1 FF B8
B1 FF B8
how many cache miss(es) would occur for the data request?

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Question 4
For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Tag 31-10 Index 9-5 a. What is the cache block size (in words)? b. How many entries does the cache have? Offset 4-0 c. What is the ratio between total bits required for such a cache implementation over the data storage bits?
Cache system B represents a 2-way set-associative mapping cache system in table 2 The system is byte-addressable and the block size is one word (4 bytes). The tag and set numbers are represented with binary numbers. The contents of words in a block are represented with hexadecimal. Tag 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 Table 2 1. What is the size of the main memory for the Cache system B? Answer= 2. What is the size of the cache memory of Cache system B? Answer = Answer= Answer = 16 Answer = Set Number 16 1011 0110 1101 1011 0110 1101 miss(es) 1011 0110 1110 1011 0110 1110 1011 0110 1111 1011 0110 1111 1011 0111 0000 3. If we request to read memory address F1 24 2D B7, what data do we get? 1011 0111 0000 1011 0111 0001 1011 0111 0001 4. If we…