Question 24 Some portion of cache system B represented a 2-way set-associative mapping cache system. The system is byte-addressable and the block size is one word (4 bytes). The tag and set number are represented with a binary numbers. The contents of words in the block are represented with hexadecimal. Tag 10 1000 0100 1001 11 1100 0100 1001 10 1000 0100 1001 11 1100 0100 1101 10 1000 0100 1001 11 1100 0100 1001 10 1000 0100 1001 11 1100 0100 1101 10 1000 0100 1001 11 1100 0100 1001 10 1000 0100 1001 11 1100 0100 1101 Set Number 0110 1101 0110 1101 0110 1110 0110 1110 0110 1111 0110 1111 0111 0000 0111 0000 0111 0001 0111 0001 0111 0010 0111 0010 00 2. What is the size of cache memory? 2016 6116 C116 4216 3216 7216 5216 Word within block 01 10 3216 A216 C216 8216 9216 8216 3216 7216 C216 2716 6116 1. What is the size of the main memory for cache system B? 4116 11 2016 6116 D116 5116 2116 D216 A216 4216 8216 6116 1216 5216 A216 5216 B216 B216 D216 C116 2116 7216 C216 D216 8216 4116 A216 5216 9216 5216 B216 3. If we request memory read from memory address F1 35 C3, what data do we read? 4. If we request memory read from memory address A1 25 BA, what data do we read?

Question 24 Some portion of cache system B represented a 2-way set-associative mapping cache system. The system is byte-addressable and the block size is one word (4 bytes). The tag and set number are represented with a binary numbers. The contents of words in the block are represented with hexadecimal. Tag 10 1000 0100 1001 11 1100 0100 1001 10 1000 0100 1001 11 1100 0100 1101 10 1000 0100 1001 11 1100 0100 1001 10 1000 0100 1001 11 1100 0100 1101 10 1000 0100 1001 11 1100 0100 1001 10 1000 0100 1001 11 1100 0100 1101 Set Number 0110 1101 0110 1101 0110 1110 0110 1110 0110 1111 0110 1111 0111 0000 0111 0000 0111 0001 0111 0001 0111 0010 0111 0010 00 2. What is the size of cache memory? 2016 6116 C116 4216 3216 7216 5216 Word within block 01 10 3216 A216 C216 8216 9216 8216 3216 7216 C216 2716 6116 1. What is the size of the main memory for cache system B? 4116 11 2016 6116 D116 5116 2116 D216 A216 4216 8216 6116 1216 5216 A216 5216 B216 B216 D216 C116 2116 7216 C216 D216 8216 4116 A216 5216 9216 5216 B216 3. If we request memory read from memory address F1 35 C3, what data do we read? 4. If we request memory read from memory address A1 25 BA, what data do we read?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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I have a little bit problem with my late quiz for computer architecture, I get the answer from my lecturer but I still don't feel fully understand, can I ask for some help: In a computer system, the memory has 32 blocks and the cache has 8 blocks. Assume there is only one word per block with 4 bytes in one word. The reference sequence in terms of word location is 0, 2, 4, 10, 5, 12, 8, 18, 13. If the cache is direct-mapped, how many misses do we have if the cache is initially empty? Can you give the hit or miss for each reference?
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